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Benjamin Herrenschmidt b58ff724f6 litedram: Add stash buffer to the L2 cache wishbone interface ... This breaks the long stall signal coming back to the processor and helps improve overall timing. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
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fusesoc-add-files.py	litedram: Remove old "VexRiscV" based initializations	5 years ago
litedram-wrapper-l2.vhdl	litedram: Add stash buffer to the L2 cache wishbone interface	5 years ago
sim_dram_verilate.mk	litedram: Add simulation support	5 years ago
sim_litedram.vhdl	litedram: Add simulation support	5 years ago
sim_litedram_c.cpp	litedram: Add simulation support	5 years ago
wave.gtkw	litedram: Add an L2 cache with store queue	5 years ago
wave.opt	litedram: Add an L2 cache with store queue	5 years ago
wave_tb.gtkw	litedram: Test bench	5 years ago