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90 lines
2.2 KiB
VHDL
90 lines
2.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.common.all;
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entity writeback is
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port (
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clk : in std_ulogic;
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e_in : in Execute2ToWritebackType;
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l_in : in Loadstore2ToWritebackType;
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m_in : in MultiplyToWritebackType;
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w_out : out WritebackToRegisterFileType;
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c_out : out WritebackToCrFileType;
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complete_out : out std_ulogic
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);
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end entity writeback;
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architecture behaviour of writeback is
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signal e : Execute2ToWritebackType;
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signal l : Loadstore2ToWritebackType;
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signal m : MultiplyToWritebackType;
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signal w_tmp : WritebackToRegisterFileType;
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signal c_tmp : WritebackToCrFileType;
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begin
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writeback_0: process(clk)
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begin
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if rising_edge(clk) then
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e <= e_in;
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l <= l_in;
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m <= m_in;
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end if;
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end process;
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w_out <= w_tmp;
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c_out <= c_tmp;
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complete_out <= '1' when e.valid or l.valid or m.valid else '0';
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writeback_1: process(all)
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begin
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--assert (unsigned(w.valid) + unsigned(l.valid) + unsigned(m.valid)) <= 1;
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--assert not(w.write_enable = '1' and l.write_enable = '1');
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w_tmp <= WritebackToRegisterFileInit;
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c_tmp <= WritebackToCrFileInit;
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if e.valid = '1' then
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if e.write_enable = '1' then
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w_tmp.write_reg <= e.write_reg;
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w_tmp.write_data <= e.write_data;
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w_tmp.write_enable <= '1';
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end if;
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if e.write_cr_enable = '1' then
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c_tmp.write_cr_enable <= '1';
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c_tmp.write_cr_mask <= e.write_cr_mask;
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c_tmp.write_cr_data <= e.write_cr_data;
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end if;
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end if;
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if l.valid = '1' and l.write_enable = '1' then
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w_tmp.write_reg <= l.write_reg;
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w_tmp.write_data <= l.write_data;
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w_tmp.write_enable <= '1';
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end if;
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if l.valid = '1' and l.write_enable2 = '1' then
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w_tmp.write_reg2 <= l.write_reg2;
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w_tmp.write_data2 <= l.write_data2;
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w_tmp.write_enable2 <= '1';
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end if;
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if m.valid = '1' then
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if m.write_reg_enable = '1' then
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w_tmp.write_enable <= '1';
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w_tmp.write_reg <= m.write_reg_nr;
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w_tmp.write_data <= m.write_reg_data;
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end if;
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if m.write_cr_enable = '1' then
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c_tmp.write_cr_enable <= '1';
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c_tmp.write_cr_mask <= m.write_cr_mask;
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c_tmp.write_cr_data <= m.write_cr_data;
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end if;
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end if;
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end process;
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end;
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