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bc0f7cf236
Experimenting with using ghdl to do VHDL to Verilog conversion (instead
of ghdl+yosys), verilator complains that a signal is a SystemVerilog
keyword:
%Error: microwatt.v:15013:18: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.
... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.
We could probably make this go away by disabling SystemVerilog, but
it's easy to rename the signal in question. Rename di at the same
time.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
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3 years ago | |
|---|---|---|
| .. | ||
| LICENSE | 5 years ago | |
| acorn-cle-215.xdc | 4 years ago | |
| arty_a7.xdc | 3 years ago | |
| clk_gen_bypass.vhd | 5 years ago | |
| clk_gen_ecp5.vhd | 3 years ago | |
| clk_gen_mcmm.vhd | 3 years ago | |
| clk_gen_plle2.vhd | 3 years ago | |
| cmod_a7-35.xdc | 3 years ago | |
| firmware.hex | 5 years ago | |
| fpga-random.vhdl | 4 years ago | |
| fpga-random.xdc | 4 years ago | |
| genesys2.xdc | 3 years ago | |
| hello_world.hex | 4 years ago | |
| main_bram.vhdl | 3 years ago | |
| nexys-video.xdc | 3 years ago | |
| nexys_a7.xdc | 3 years ago | |
| pp_fifo.vhd | 4 years ago | |
| pp_soc_uart.vhd | 4 years ago | |
| pp_utilities.vhd | 5 years ago | |
| soc_reset.vhdl | 4 years ago | |
| soc_reset_tb.vhdl | 4 years ago | |
| top-acorn-cle-215.vhdl | 4 years ago | |
| top-arty.vhdl | 3 years ago | |
| top-generic.vhdl | 3 years ago | |
| top-genesys2.vhdl | 4 years ago | |
| top-nexys-video.vhdl | 3 years ago | |