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240 lines
10 KiB
Plaintext
240 lines
10 KiB
Plaintext
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
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create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }];
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set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ext_rst }];
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set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }];
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set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }];
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##Pmod Header JC: UART (bottom)
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set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }];
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set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }];
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set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }];
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set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }];
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# LEDs
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set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }];
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set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }];
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set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }];
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# DRAM (generated by LiteX)
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## ddram:0.a
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set_property LOC R2 [get_ports ddram_a[0]]
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set_property SLEW FAST [get_ports ddram_a[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]]
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## ddram:0.a
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set_property LOC M6 [get_ports ddram_a[1]]
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set_property SLEW FAST [get_ports ddram_a[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]]
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## ddram:0.a
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set_property LOC N4 [get_ports ddram_a[2]]
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set_property SLEW FAST [get_ports ddram_a[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]]
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## ddram:0.a
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set_property LOC T1 [get_ports ddram_a[3]]
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set_property SLEW FAST [get_ports ddram_a[3]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]]
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## ddram:0.a
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set_property LOC N6 [get_ports ddram_a[4]]
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set_property SLEW FAST [get_ports ddram_a[4]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]]
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## ddram:0.a
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set_property LOC R7 [get_ports ddram_a[5]]
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set_property SLEW FAST [get_ports ddram_a[5]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]]
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## ddram:0.a
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set_property LOC V6 [get_ports ddram_a[6]]
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set_property SLEW FAST [get_ports ddram_a[6]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]]
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## ddram:0.a
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set_property LOC U7 [get_ports ddram_a[7]]
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set_property SLEW FAST [get_ports ddram_a[7]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]]
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## ddram:0.a
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set_property LOC R8 [get_ports ddram_a[8]]
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set_property SLEW FAST [get_ports ddram_a[8]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]]
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## ddram:0.a
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set_property LOC V7 [get_ports ddram_a[9]]
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set_property SLEW FAST [get_ports ddram_a[9]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]]
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## ddram:0.a
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set_property LOC R6 [get_ports ddram_a[10]]
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set_property SLEW FAST [get_ports ddram_a[10]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]]
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## ddram:0.a
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set_property LOC U6 [get_ports ddram_a[11]]
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set_property SLEW FAST [get_ports ddram_a[11]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]]
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## ddram:0.a
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set_property LOC T6 [get_ports ddram_a[12]]
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set_property SLEW FAST [get_ports ddram_a[12]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]]
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## ddram:0.a
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set_property LOC T8 [get_ports ddram_a[13]]
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set_property SLEW FAST [get_ports ddram_a[13]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]]
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## ddram:0.ba
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set_property LOC R1 [get_ports ddram_ba[0]]
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set_property SLEW FAST [get_ports ddram_ba[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]]
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## ddram:0.ba
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set_property LOC P4 [get_ports ddram_ba[1]]
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set_property SLEW FAST [get_ports ddram_ba[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]]
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## ddram:0.ba
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set_property LOC P2 [get_ports ddram_ba[2]]
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set_property SLEW FAST [get_ports ddram_ba[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]]
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## ddram:0.ras_n
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set_property LOC P3 [get_ports ddram_ras_n]
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set_property SLEW FAST [get_ports ddram_ras_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n]
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## ddram:0.cas_n
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set_property LOC M4 [get_ports ddram_cas_n]
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set_property SLEW FAST [get_ports ddram_cas_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n]
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## ddram:0.we_n
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set_property LOC P5 [get_ports ddram_we_n]
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set_property SLEW FAST [get_ports ddram_we_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_we_n]
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## ddram:0.cs_n
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set_property LOC U8 [get_ports ddram_cs_n]
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set_property SLEW FAST [get_ports ddram_cs_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n]
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## ddram:0.dm
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set_property LOC L1 [get_ports ddram_dm[0]]
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set_property SLEW FAST [get_ports ddram_dm[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]]
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## ddram:0.dm
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set_property LOC U1 [get_ports ddram_dm[1]]
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set_property SLEW FAST [get_ports ddram_dm[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]]
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## ddram:0.dq
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set_property LOC K5 [get_ports ddram_dq[0]]
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set_property SLEW FAST [get_ports ddram_dq[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]]
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## ddram:0.dq
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set_property LOC L3 [get_ports ddram_dq[1]]
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set_property SLEW FAST [get_ports ddram_dq[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]]
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## ddram:0.dq
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set_property LOC K3 [get_ports ddram_dq[2]]
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set_property SLEW FAST [get_ports ddram_dq[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]]
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## ddram:0.dq
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set_property LOC L6 [get_ports ddram_dq[3]]
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set_property SLEW FAST [get_ports ddram_dq[3]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]]
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## ddram:0.dq
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set_property LOC M3 [get_ports ddram_dq[4]]
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set_property SLEW FAST [get_ports ddram_dq[4]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]]
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## ddram:0.dq
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set_property LOC M1 [get_ports ddram_dq[5]]
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set_property SLEW FAST [get_ports ddram_dq[5]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]]
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## ddram:0.dq
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set_property LOC L4 [get_ports ddram_dq[6]]
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set_property SLEW FAST [get_ports ddram_dq[6]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]]
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## ddram:0.dq
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set_property LOC M2 [get_ports ddram_dq[7]]
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set_property SLEW FAST [get_ports ddram_dq[7]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]]
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## ddram:0.dq
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set_property LOC V4 [get_ports ddram_dq[8]]
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set_property SLEW FAST [get_ports ddram_dq[8]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]]
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## ddram:0.dq
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set_property LOC T5 [get_ports ddram_dq[9]]
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set_property SLEW FAST [get_ports ddram_dq[9]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]]
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## ddram:0.dq
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set_property LOC U4 [get_ports ddram_dq[10]]
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set_property SLEW FAST [get_ports ddram_dq[10]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]]
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## ddram:0.dq
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set_property LOC V5 [get_ports ddram_dq[11]]
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set_property SLEW FAST [get_ports ddram_dq[11]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]]
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## ddram:0.dq
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set_property LOC V1 [get_ports ddram_dq[12]]
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set_property SLEW FAST [get_ports ddram_dq[12]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]]
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## ddram:0.dq
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set_property LOC T3 [get_ports ddram_dq[13]]
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set_property SLEW FAST [get_ports ddram_dq[13]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]]
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## ddram:0.dq
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set_property LOC U3 [get_ports ddram_dq[14]]
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set_property SLEW FAST [get_ports ddram_dq[14]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]]
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## ddram:0.dq
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set_property LOC R3 [get_ports ddram_dq[15]]
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set_property SLEW FAST [get_ports ddram_dq[15]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]]
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## ddram:0.dqs_p
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set_property LOC N2 [get_ports ddram_dqs_p[0]]
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set_property SLEW FAST [get_ports ddram_dqs_p[0]]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]]
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## ddram:0.dqs_p
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set_property LOC U2 [get_ports ddram_dqs_p[1]]
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set_property SLEW FAST [get_ports ddram_dqs_p[1]]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]]
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## ddram:0.dqs_n
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set_property LOC N1 [get_ports ddram_dqs_n[0]]
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set_property SLEW FAST [get_ports ddram_dqs_n[0]]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]]
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## ddram:0.dqs_n
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set_property LOC V2 [get_ports ddram_dqs_n[1]]
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set_property SLEW FAST [get_ports ddram_dqs_n[1]]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]]
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## ddram:0.clk_p
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set_property LOC U9 [get_ports ddram_clk_p]
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set_property SLEW FAST [get_ports ddram_clk_p]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p]
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## ddram:0.clk_n
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set_property LOC V9 [get_ports ddram_clk_n]
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set_property SLEW FAST [get_ports ddram_clk_n]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n]
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## ddram:0.cke
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set_property LOC N5 [get_ports ddram_cke]
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set_property SLEW FAST [get_ports ddram_cke]
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set_property IOSTANDARD SSTL135 [get_ports ddram_cke]
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## ddram:0.odt
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set_property LOC R5 [get_ports ddram_odt]
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set_property SLEW FAST [get_ports ddram_odt]
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set_property IOSTANDARD SSTL135 [get_ports ddram_odt]
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## ddram:0.reset_n
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set_property LOC K6 [get_ports ddram_reset_n]
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set_property SLEW FAST [get_ports ddram_reset_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n]
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#Internal VREF
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set_property INTERNAL_VREF 0.675 [get_iobanks 34]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CFGBVS VCCO [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
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set_property CONFIG_MODE SPIx4 [current_design]
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