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microwatt/litedram/gen-src
Michael Neuling 57604c1a6e
Merge pull request #213 from ozbenh/uart16550
Add support for standard 16550 style UART
4 years ago
..
sdram_init Merge pull request #213 from ozbenh/uart16550 4 years ago
arty.yml litedram: Remove old "VexRiscV" based initializations 4 years ago
dram-init-mem.vhdl litedram: Fix DRAM init mem using too many address bits 4 years ago
generate.py litedram: Remove old "VexRiscV" based initializations 4 years ago
nexys-video.yml litedram: Remove old "VexRiscV" based initializations 4 years ago
no-init-mem.vhdl litedram: Split the init memory from the main wrapper 5 years ago
sim.yml litedram: Remove old "VexRiscV" based initializations 4 years ago