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Benjamin Herrenschmidt bf7def5503 soc: Don't require dram wishbones signals to be wired by toplevel ... Currently, when not using litedram, the top level still has to hook up "dummy" wishbones to the main dram and control dram busses coming out of the SoC and provide ack signals. Instead, make the SoC generate the acks internally when not using litedram and use defaults to make the wiring entirely optional. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		4 years ago
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LICENSE	Initial import of microwatt	5 years ago
arty_a7.xdc	spi: Add SPI Flash controller	4 years ago
clk_gen_bypass.vhd	Fix clk_gen_bypass	5 years ago
clk_gen_mcmm.vhd	Improve PLL/MMCM clocks configuration	5 years ago
clk_gen_plle2.vhd	Improve PLL/MMCM clocks configuration	5 years ago
cmod_a7-35.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
firmware.hex	Add a few more FPGA related files	5 years ago
hello_world.hex	hello_world: Use new headers and frequency from syscon	4 years ago
main_bram.vhdl	Fix some ghdlsynth issues with fpga_bram	4 years ago
nexys-video.xdc	spi: Add SPI Flash controller	4 years ago
nexys_a7.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
pp_fifo.vhd	pp_fifo: Fix full fifo losing all data on simultaneous push & pop	4 years ago
pp_soc_uart.vhd	uart: Remove combinational loops on ack and stall signal	4 years ago
pp_utilities.vhd	Initial import of microwatt	5 years ago
soc_reset.vhdl	soc_reset: Use counters, add synchronizers	4 years ago
soc_reset_tb.vhdl	Exit cleanly from testbench on success	4 years ago
top-arty.vhdl	soc: Remove unused RESET_LOW generic	4 years ago
top-generic.vhdl	soc: Don't require dram wishbones signals to be wired by toplevel	4 years ago
top-nexys-video.vhdl	soc: Remove unused RESET_LOW generic	4 years ago