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205 lines
7.2 KiB
VHDL
205 lines
7.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity fetch1 is
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generic(
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RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0');
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ALT_RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0');
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HAS_BTC : boolean := true
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);
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port(
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clk : in std_ulogic;
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rst : in std_ulogic;
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-- Control inputs:
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stall_in : in std_ulogic;
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flush_in : in std_ulogic;
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inval_btc : in std_ulogic;
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stop_in : in std_ulogic;
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alt_reset_in : in std_ulogic;
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-- redirect from writeback unit
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w_in : in WritebackToFetch1Type;
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-- redirect from decode1
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d_in : in Decode1ToFetch1Type;
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-- Request to icache
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i_out : out Fetch1ToIcacheType;
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-- outputs to logger
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log_out : out std_ulogic_vector(42 downto 0)
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);
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end entity fetch1;
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architecture behaviour of fetch1 is
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type reg_internal_t is record
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mode_32bit: std_ulogic;
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rd_is_niap4: std_ulogic;
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predicted: std_ulogic;
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predicted_nia: std_ulogic_vector(63 downto 0);
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end record;
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signal r, r_next : Fetch1ToIcacheType;
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signal r_int, r_next_int : reg_internal_t;
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signal advance_nia : std_ulogic;
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signal log_nia : std_ulogic_vector(42 downto 0);
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constant BTC_ADDR_BITS : integer := 10;
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constant BTC_TAG_BITS : integer := 62 - BTC_ADDR_BITS;
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constant BTC_TARGET_BITS : integer := 62;
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constant BTC_SIZE : integer := 2 ** BTC_ADDR_BITS;
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constant BTC_WIDTH : integer := BTC_TAG_BITS + BTC_TARGET_BITS;
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type btc_mem_type is array (0 to BTC_SIZE - 1) of std_ulogic_vector(BTC_WIDTH - 1 downto 0);
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signal btc_rd_data : std_ulogic_vector(BTC_WIDTH - 1 downto 0) := (others => '0');
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signal btc_rd_valid : std_ulogic := '0';
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begin
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regs : process(clk)
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begin
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if rising_edge(clk) then
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log_nia <= r.nia(63) & r.nia(43 downto 2);
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if r /= r_next then
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report "fetch1 rst:" & std_ulogic'image(rst) &
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" IR:" & std_ulogic'image(r_next.virt_mode) &
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" P:" & std_ulogic'image(r_next.priv_mode) &
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" E:" & std_ulogic'image(r_next.big_endian) &
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" 32:" & std_ulogic'image(r_next_int.mode_32bit) &
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" R:" & std_ulogic'image(w_in.redirect) & std_ulogic'image(d_in.redirect) &
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" S:" & std_ulogic'image(stall_in) &
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" T:" & std_ulogic'image(stop_in) &
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" nia:" & to_hstring(r_next.nia);
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end if;
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if rst = '1' or w_in.redirect = '1' or d_in.redirect = '1' or stall_in = '0' then
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r.virt_mode <= r_next.virt_mode;
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r.priv_mode <= r_next.priv_mode;
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r.big_endian <= r_next.big_endian;
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r_int.mode_32bit <= r_next_int.mode_32bit;
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end if;
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if advance_nia = '1' then
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r.predicted <= r_next.predicted;
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r.nia <= r_next.nia;
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r_int.predicted <= r_next_int.predicted;
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r_int.predicted_nia <= r_next_int.predicted_nia;
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r_int.rd_is_niap4 <= r_next.sequential;
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end if;
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r.sequential <= r_next.sequential and advance_nia;
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-- always send the up-to-date stop mark and req
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r.stop_mark <= stop_in;
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r.req <= not rst;
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end if;
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end process;
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log_out <= log_nia;
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btc : if HAS_BTC generate
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signal btc_memory : btc_mem_type;
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attribute ram_style : string;
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attribute ram_style of btc_memory : signal is "block";
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signal btc_valids : std_ulogic_vector(BTC_SIZE - 1 downto 0);
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attribute ram_style of btc_valids : signal is "distributed";
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signal btc_wr : std_ulogic;
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signal btc_wr_data : std_ulogic_vector(BTC_WIDTH - 1 downto 0);
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signal btc_wr_addr : std_ulogic_vector(BTC_ADDR_BITS - 1 downto 0);
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signal btc_wr_v : std_ulogic;
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begin
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btc_wr_data <= w_in.br_nia(63 downto BTC_ADDR_BITS + 2) &
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w_in.redirect_nia(63 downto 2);
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btc_wr_addr <= w_in.br_nia(BTC_ADDR_BITS + 1 downto 2);
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btc_wr <= w_in.br_last;
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btc_wr_v <= w_in.br_taken;
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btc_ram : process(clk)
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variable raddr : unsigned(BTC_ADDR_BITS - 1 downto 0);
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begin
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if rising_edge(clk) then
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raddr := unsigned(r.nia(BTC_ADDR_BITS + 1 downto 2)) +
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to_unsigned(2, BTC_ADDR_BITS);
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if advance_nia = '1' then
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btc_rd_data <= btc_memory(to_integer(raddr));
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btc_rd_valid <= btc_valids(to_integer(raddr));
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end if;
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if btc_wr = '1' then
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btc_memory(to_integer(unsigned(btc_wr_addr))) <= btc_wr_data;
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end if;
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if inval_btc = '1' or rst = '1' then
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btc_valids <= (others => '0');
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elsif btc_wr = '1' then
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btc_valids(to_integer(unsigned(btc_wr_addr))) <= btc_wr_v;
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end if;
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end if;
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end process;
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end generate;
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comb : process(all)
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variable v : Fetch1ToIcacheType;
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variable v_int : reg_internal_t;
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begin
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v := r;
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v_int := r_int;
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v.sequential := '0';
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v.predicted := '0';
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v_int.predicted := '0';
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if rst = '1' then
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if alt_reset_in = '1' then
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v.nia := ALT_RESET_ADDRESS;
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else
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v.nia := RESET_ADDRESS;
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end if;
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v.virt_mode := '0';
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v.priv_mode := '1';
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v.big_endian := '0';
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v_int.mode_32bit := '0';
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v_int.predicted_nia := (others => '0');
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elsif w_in.redirect = '1' then
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v.nia := w_in.redirect_nia(63 downto 2) & "00";
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if w_in.mode_32bit = '1' then
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v.nia(63 downto 32) := (others => '0');
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end if;
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v.virt_mode := w_in.virt_mode;
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v.priv_mode := w_in.priv_mode;
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v.big_endian := w_in.big_endian;
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v_int.mode_32bit := w_in.mode_32bit;
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elsif d_in.redirect = '1' then
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v.nia := d_in.redirect_nia(63 downto 2) & "00";
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if r_int.mode_32bit = '1' then
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v.nia(63 downto 32) := (others => '0');
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end if;
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elsif r_int.predicted = '1' then
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v.nia := r_int.predicted_nia;
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v.predicted := '1';
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else
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v.sequential := '1';
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v.nia := std_ulogic_vector(unsigned(r.nia) + 4);
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if r_int.mode_32bit = '1' then
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v.nia(63 downto 32) := x"00000000";
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end if;
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if btc_rd_valid = '1' and r_int.rd_is_niap4 = '1' and
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btc_rd_data(BTC_WIDTH - 1 downto BTC_TARGET_BITS)
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= v.nia(BTC_TAG_BITS + BTC_ADDR_BITS + 1 downto BTC_ADDR_BITS + 2) then
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v_int.predicted := '1';
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end if;
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end if;
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v_int.predicted_nia := btc_rd_data(BTC_TARGET_BITS - 1 downto 0) & "00";
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-- If the last NIA value went down with a stop mark, it didn't get
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-- executed, and hence we shouldn't increment NIA.
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advance_nia <= rst or w_in.redirect or d_in.redirect or (not r.stop_mark and not stall_in);
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r_next <= v;
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r_next_int <= v_int;
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-- Update outputs to the icache
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i_out <= r;
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end process;
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end architecture behaviour;
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