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320 lines
8.8 KiB
VHDL
320 lines
8.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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library work;
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use work.wishbone_types.all;
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entity toplevel is
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generic (
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MEMORY_SIZE : integer := 16384;
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RAM_INIT_FILE : string := "firmware.hex";
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CLK_FREQUENCY : positive := 100000000;
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USE_LITEDRAM : boolean := false;
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NO_BRAM : boolean := false;
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DISABLE_FLATTEN_CORE : boolean := false;
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SPI_FLASH_OFFSET : integer := 10485760;
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SPI_FLASH_DEF_CKDV : natural := 1;
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SPI_FLASH_DEF_QUAD : boolean := true;
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LOG_LENGTH : natural := 2048;
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UART_IS_16550 : boolean := true
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);
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port(
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clk200_p : in std_ulogic;
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clk200_n : in std_ulogic;
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-- P2 signals used as UART
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uart_rx : in std_ulogic;
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uart_tx : out std_ulogic;
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-- LEDs
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led0 : out std_logic;
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led1 : out std_logic;
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led2 : out std_logic;
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led3 : out std_logic;
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-- SPI
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spi_flash_cs_n : out std_ulogic;
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spi_flash_mosi : inout std_ulogic;
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spi_flash_miso : inout std_ulogic;
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spi_flash_wp_n : inout std_ulogic;
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spi_flash_hold_n : inout std_ulogic;
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-- DRAM wires
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ddram_a : out std_logic_vector(15 downto 0);
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ddram_ba : out std_logic_vector(2 downto 0);
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ddram_ras_n : out std_logic;
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ddram_cas_n : out std_logic;
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ddram_we_n : out std_logic;
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ddram_dm : out std_logic_vector(1 downto 0);
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ddram_dq : inout std_logic_vector(15 downto 0);
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ddram_dqs_p : inout std_logic_vector(1 downto 0);
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ddram_dqs_n : inout std_logic_vector(1 downto 0);
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ddram_clk_p : out std_logic;
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ddram_clk_n : out std_logic;
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ddram_cke : out std_logic;
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ddram_odt : out std_logic;
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ddram_reset_n : out std_logic
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);
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end entity toplevel;
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architecture behaviour of toplevel is
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-- Internal clock
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signal ext_clk : std_ulogic;
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-- Reset signals:
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signal soc_rst : std_ulogic;
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signal pll_rst : std_ulogic;
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-- Internal clock signals:
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signal system_clk : std_ulogic;
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signal system_clk_locked : std_ulogic;
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-- DRAM main data wishbone connection
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signal wb_dram_in : wishbone_master_out;
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signal wb_dram_out : wishbone_slave_out;
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-- DRAM control wishbone connection
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signal wb_ext_io_in : wb_io_master_out;
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signal wb_ext_io_out : wb_io_slave_out;
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signal wb_ext_is_dram_csr : std_ulogic;
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signal wb_ext_is_dram_init : std_ulogic;
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-- Control/status
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signal core_alt_reset : std_ulogic;
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-- SPI flash
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signal spi_sck : std_ulogic;
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signal spi_cs_n : std_ulogic;
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signal spi_sdat_o : std_ulogic_vector(3 downto 0);
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signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
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signal spi_sdat_i : std_ulogic_vector(3 downto 0);
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-- Fixup various memory sizes based on generics
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function get_bram_size return natural is
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begin
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if USE_LITEDRAM and NO_BRAM then
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return 0;
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else
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return MEMORY_SIZE;
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end if;
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end function;
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function get_payload_size return natural is
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begin
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if USE_LITEDRAM and NO_BRAM then
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return MEMORY_SIZE;
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else
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return 0;
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end if;
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end function;
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constant BRAM_SIZE : natural := get_bram_size;
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constant PAYLOAD_SIZE : natural := get_payload_size;
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begin
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-- Main SoC
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soc0: entity work.soc
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generic map(
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MEMORY_SIZE => BRAM_SIZE,
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RAM_INIT_FILE => RAM_INIT_FILE,
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SIM => false,
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CLK_FREQ => CLK_FREQUENCY,
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HAS_DRAM => USE_LITEDRAM,
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DRAM_SIZE => 1024 * 1024 * 1024,
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DRAM_INIT_SIZE => PAYLOAD_SIZE,
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DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
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HAS_SPI_FLASH => true,
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SPI_FLASH_DLINES => 4,
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SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
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SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
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SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
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LOG_LENGTH => LOG_LENGTH,
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UART0_IS_16550 => UART_IS_16550
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)
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port map (
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-- System signals
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system_clk => system_clk,
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rst => soc_rst,
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-- UART signals
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uart0_txd => uart_tx,
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uart0_rxd => uart_rx,
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-- SPI signals
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spi_flash_sck => spi_sck,
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spi_flash_cs_n => spi_cs_n,
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spi_flash_sdat_o => spi_sdat_o,
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spi_flash_sdat_oe => spi_sdat_oe,
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spi_flash_sdat_i => spi_sdat_i,
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-- DRAM wishbone
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wb_dram_in => wb_dram_in,
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wb_dram_out => wb_dram_out,
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wb_ext_io_in => wb_ext_io_in,
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wb_ext_io_out => wb_ext_io_out,
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wb_ext_is_dram_csr => wb_ext_is_dram_csr,
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wb_ext_is_dram_init => wb_ext_is_dram_init,
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alt_reset => core_alt_reset
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);
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-- SPI Flash. The SPI clk needs to be fed through the STARTUPE2
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-- primitive of the FPGA as it's not a normal pin
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--
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spi_flash_cs_n <= spi_cs_n;
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spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
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spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
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spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
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spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
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spi_sdat_i(0) <= spi_flash_mosi;
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spi_sdat_i(1) <= spi_flash_miso;
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spi_sdat_i(2) <= spi_flash_wp_n;
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spi_sdat_i(3) <= spi_flash_hold_n;
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STARTUPE2_INST: STARTUPE2
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port map (
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CLK => '0',
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GSR => '0',
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GTS => '0',
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KEYCLEARB => '0',
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PACK => '0',
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USRCCLKO => spi_sck,
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USRCCLKTS => '0',
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USRDONEO => '1',
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USRDONETS => '0'
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);
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clk200: IBUFDS
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port map (
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i => clk200_p,
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ib => clk200_n,
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o => ext_clk
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);
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nodram: if not USE_LITEDRAM generate
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signal ddram_clk_dummy : std_ulogic;
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begin
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => false
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => system_clk_locked,
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ext_rst_in => '0',
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pll_rst_out => pll_rst,
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rst_out => soc_rst
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);
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clkgen: entity work.clock_generator
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generic map(
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CLK_INPUT_HZ => 200000000,
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CLK_OUTPUT_HZ => CLK_FREQUENCY
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)
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port map(
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ext_clk => ext_clk,
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pll_rst_in => pll_rst,
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pll_clk_out => system_clk,
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pll_locked_out => system_clk_locked
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);
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led0 <= soc_rst;
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led1 <= pll_rst;
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led2 <= not system_clk_locked;
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led3 <= '0';
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core_alt_reset <= '0';
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-- Vivado barfs on those differential signals if left
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-- unconnected. So instanciate a diff. buffer and feed
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-- it a constant '0'.
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dummy_dram_clk: OBUFDS
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port map (
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O => ddram_clk_p,
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OB => ddram_clk_n,
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I => ddram_clk_dummy
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);
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ddram_clk_dummy <= '0';
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end generate;
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has_dram: if USE_LITEDRAM generate
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signal dram_init_done : std_ulogic;
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signal dram_init_error : std_ulogic;
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signal dram_sys_rst : std_ulogic;
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begin
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-- Eventually dig out the frequency from the generator
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-- but for now, assert it's 100Mhz
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assert CLK_FREQUENCY = 100000000;
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => false,
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PLL_RESET_BITS => 18,
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SOC_RESET_BITS => 1
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => '1',
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ext_rst_in => '0',
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pll_rst_out => pll_rst,
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rst_out => open
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);
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dram: entity work.litedram_wrapper
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generic map(
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DRAM_ABITS => 26,
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DRAM_ALINES => 16,
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DRAM_DLINES => 16,
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DRAM_PORT_WIDTH => 128,
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PAYLOAD_FILE => RAM_INIT_FILE,
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PAYLOAD_SIZE => PAYLOAD_SIZE
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)
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port map(
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clk_in => ext_clk,
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rst => pll_rst,
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system_clk => system_clk,
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system_reset => soc_rst,
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core_alt_reset => core_alt_reset,
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pll_locked => system_clk_locked,
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wb_in => wb_dram_in,
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wb_out => wb_dram_out,
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wb_ctrl_in => wb_ext_io_in,
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wb_ctrl_out => wb_ext_io_out,
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wb_ctrl_is_csr => wb_ext_is_dram_csr,
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wb_ctrl_is_init => wb_ext_is_dram_init,
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init_done => dram_init_done,
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init_error => dram_init_error,
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ddram_a => ddram_a,
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ddram_ba => ddram_ba,
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ddram_ras_n => ddram_ras_n,
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ddram_cas_n => ddram_cas_n,
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ddram_we_n => ddram_we_n,
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ddram_cs_n => open,
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ddram_dm => ddram_dm,
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ddram_dq => ddram_dq,
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ddram_dqs_p => ddram_dqs_p,
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ddram_dqs_n => ddram_dqs_n,
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ddram_clk_p => ddram_clk_p,
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ddram_clk_n => ddram_clk_n,
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ddram_cke => ddram_cke,
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ddram_odt => ddram_odt,
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ddram_reset_n => ddram_reset_n
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);
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led0 <= soc_rst;
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led1 <= pll_rst;
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led2 <= not dram_init_done or dram_init_error;
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led3 <= not dram_init_error; -- Make it blink ?
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end generate;
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end architecture behaviour;
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