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578 lines
21 KiB
VHDL
578 lines
21 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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library work;
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use work.wishbone_types.all;
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entity toplevel is
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generic (
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MEMORY_SIZE : integer := 16384;
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RAM_INIT_FILE : string := "firmware.hex";
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RESET_LOW : boolean := true;
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CLK_FREQUENCY : positive := 100000000;
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HAS_FPU : boolean := true;
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HAS_BTC : boolean := true;
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USE_LITEDRAM : boolean := false;
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NO_BRAM : boolean := false;
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DISABLE_FLATTEN_CORE : boolean := false;
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SPI_FLASH_OFFSET : integer := 4194304;
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SPI_FLASH_DEF_CKDV : natural := 1;
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SPI_FLASH_DEF_QUAD : boolean := true;
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LOG_LENGTH : natural := 512;
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USE_LITEETH : boolean := false;
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UART_IS_16550 : boolean := true;
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HAS_UART1 : boolean := false;
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USE_LITESDCARD : boolean := false;
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HAS_GPIO : boolean := false;
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NGPIO : natural := 32
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);
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port(
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ext_clk : in std_ulogic;
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ext_rst_n : in std_ulogic;
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-- UART0 signals:
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uart_main_tx : out std_ulogic;
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uart_main_rx : in std_ulogic;
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-- LEDs
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led0_n : out std_ulogic;
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led1_n : out std_ulogic;
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-- SPI
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spi_flash_cs_n : out std_ulogic;
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spi_flash_mosi : inout std_ulogic;
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spi_flash_miso : inout std_ulogic;
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spi_flash_wp_n : inout std_ulogic;
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spi_flash_hold_n : inout std_ulogic;
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-- Ethernet
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eth_clocks_tx : in std_ulogic;
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eth_clocks_gtx : out std_ulogic;
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eth_clocks_rx : in std_ulogic;
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eth_rst_n : out std_ulogic;
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eth_mdio : inout std_ulogic;
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eth_mdc : out std_ulogic;
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eth_rx_dv : in std_ulogic;
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eth_rx_er : in std_ulogic;
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eth_rx_data : in std_ulogic_vector(7 downto 0);
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eth_tx_en : out std_ulogic;
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eth_tx_er : out std_ulogic;
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eth_tx_data : out std_ulogic_vector(7 downto 0);
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eth_col : in std_ulogic;
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eth_crs : in std_ulogic;
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-- SD card
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sdcard_data : inout std_ulogic_vector(3 downto 0);
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sdcard_cmd : inout std_ulogic;
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sdcard_clk : out std_ulogic;
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sdcard_cd : in std_ulogic;
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-- DRAM wires
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ddram_a : out std_ulogic_vector(13 downto 0);
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ddram_ba : out std_ulogic_vector(2 downto 0);
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ddram_ras_n : out std_ulogic;
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ddram_cas_n : out std_ulogic;
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ddram_we_n : out std_ulogic;
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ddram_dm : out std_ulogic_vector(1 downto 0);
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ddram_dq : inout std_ulogic_vector(15 downto 0);
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ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
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ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
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ddram_clk_p : out std_ulogic;
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ddram_clk_n : out std_ulogic;
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ddram_cke : out std_ulogic;
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ddram_odt : out std_ulogic;
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ddram_reset_n : out std_ulogic
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);
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end entity toplevel;
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architecture behaviour of toplevel is
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-- Reset signals:
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signal soc_rst : std_ulogic;
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signal pll_rst : std_ulogic;
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-- Internal clock signals:
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signal system_clk : std_ulogic;
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signal system_clk_locked : std_ulogic;
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-- External IOs from the SoC
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signal wb_ext_io_in : wb_io_master_out;
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signal wb_ext_io_out : wb_io_slave_out;
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signal wb_ext_is_dram_csr : std_ulogic;
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signal wb_ext_is_dram_init : std_ulogic;
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signal wb_ext_is_eth : std_ulogic;
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signal wb_ext_is_sdcard : std_ulogic;
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-- DRAM main data wishbone connection
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signal wb_dram_in : wishbone_master_out;
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signal wb_dram_out : wishbone_slave_out;
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-- DRAM control wishbone connection
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signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init;
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-- LiteEth connection
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signal ext_irq_eth : std_ulogic;
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signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init;
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-- LiteSDCard connection
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signal ext_irq_sdcard : std_ulogic := '0';
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signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init;
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signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init;
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signal wb_sddma_in : wb_io_slave_out;
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signal wb_sddma_nr : wb_io_master_out;
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signal wb_sddma_ir : wb_io_slave_out;
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-- for conversion from non-pipelined wishbone to pipelined
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signal wb_sddma_stb_sent : std_ulogic;
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-- SPI flash
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signal spi_sck : std_ulogic;
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signal spi_cs_n : std_ulogic;
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signal spi_sdat_o : std_ulogic_vector(3 downto 0);
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signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
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signal spi_sdat_i : std_ulogic_vector(3 downto 0);
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-- ddram clock signals as vectors
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signal ddram_clk_p_vec : std_ulogic_vector(0 downto 0);
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signal ddram_clk_n_vec : std_ulogic_vector(0 downto 0);
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-- Fixup various memory sizes based on generics
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function get_bram_size return natural is
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begin
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if USE_LITEDRAM and NO_BRAM then
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return 0;
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else
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return MEMORY_SIZE;
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end if;
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end function;
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function get_payload_size return natural is
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begin
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if USE_LITEDRAM and NO_BRAM then
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return MEMORY_SIZE;
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else
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return 0;
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end if;
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end function;
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constant BRAM_SIZE : natural := get_bram_size;
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constant PAYLOAD_SIZE : natural := get_payload_size;
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begin
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-- Main SoC
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soc0: entity work.soc
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generic map(
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MEMORY_SIZE => BRAM_SIZE,
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RAM_INIT_FILE => RAM_INIT_FILE,
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SIM => false,
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CLK_FREQ => CLK_FREQUENCY,
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HAS_FPU => HAS_FPU,
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HAS_BTC => HAS_BTC,
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HAS_DRAM => USE_LITEDRAM,
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DRAM_SIZE => 256 * 1024 * 1024,
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DRAM_INIT_SIZE => PAYLOAD_SIZE,
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DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
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HAS_SPI_FLASH => true,
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SPI_FLASH_DLINES => 4,
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SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
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SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
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SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
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LOG_LENGTH => LOG_LENGTH,
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HAS_LITEETH => USE_LITEETH,
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UART0_IS_16550 => UART_IS_16550,
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HAS_UART1 => HAS_UART1,
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HAS_SD_CARD => USE_LITESDCARD,
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HAS_GPIO => HAS_GPIO,
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NGPIO => NGPIO
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)
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port map (
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-- System signals
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system_clk => system_clk,
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rst => soc_rst,
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-- UART signals
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uart0_txd => uart_main_tx,
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uart0_rxd => uart_main_rx,
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-- SPI signals
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spi_flash_sck => spi_sck,
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spi_flash_cs_n => spi_cs_n,
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spi_flash_sdat_o => spi_sdat_o,
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spi_flash_sdat_oe => spi_sdat_oe,
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spi_flash_sdat_i => spi_sdat_i,
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-- External interrupts
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ext_irq_eth => ext_irq_eth,
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ext_irq_sdcard => ext_irq_sdcard,
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-- DRAM wishbone
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wb_dram_in => wb_dram_in,
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wb_dram_out => wb_dram_out,
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-- IO wishbone
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wb_ext_io_in => wb_ext_io_in,
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wb_ext_io_out => wb_ext_io_out,
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wb_ext_is_dram_csr => wb_ext_is_dram_csr,
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wb_ext_is_dram_init => wb_ext_is_dram_init,
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wb_ext_is_eth => wb_ext_is_eth,
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wb_ext_is_sdcard => wb_ext_is_sdcard,
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-- DMA wishbone
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wishbone_dma_in => wb_sddma_in,
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wishbone_dma_out => wb_sddma_out
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);
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-- SPI Flash
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spi_flash_cs_n <= spi_cs_n;
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spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
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spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
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spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
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spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
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spi_sdat_i(0) <= spi_flash_mosi;
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spi_sdat_i(1) <= spi_flash_miso;
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spi_sdat_i(2) <= spi_flash_wp_n;
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spi_sdat_i(3) <= spi_flash_hold_n;
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STARTUPE2_INST: STARTUPE2
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port map (
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CLK => '0',
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GSR => '0',
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GTS => '0',
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KEYCLEARB => '0',
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PACK => '0',
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USRCCLKO => spi_sck,
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USRCCLKTS => '0',
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USRDONEO => '1',
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USRDONETS => '0'
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);
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nodram: if not USE_LITEDRAM generate
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signal ddram_clk_dummy : std_ulogic;
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begin
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => RESET_LOW
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => system_clk_locked,
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ext_rst_in => ext_rst_n,
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pll_rst_out => pll_rst,
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rst_out => soc_rst
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);
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clkgen: entity work.clock_generator
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generic map(
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CLK_INPUT_HZ => 50000000,
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CLK_OUTPUT_HZ => CLK_FREQUENCY
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)
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port map(
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ext_clk => ext_clk,
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pll_rst_in => pll_rst,
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pll_clk_out => system_clk,
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pll_locked_out => system_clk_locked
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);
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-- Vivado barfs on those differential signals if left
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-- unconnected. So instanciate a diff. buffer and feed
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-- it a constant '0'.
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dummy_dram_clk: OBUFDS
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port map (
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O => ddram_clk_p,
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OB => ddram_clk_n,
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I => ddram_clk_dummy
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);
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ddram_clk_dummy <= '0';
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end generate;
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has_dram: if USE_LITEDRAM generate
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signal dram_init_done : std_ulogic;
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signal dram_init_error : std_ulogic;
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signal dram_sys_rst : std_ulogic;
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signal rst_gen_rst : std_ulogic;
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begin
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-- Eventually dig out the frequency from the generator
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-- but for now, assert it's 100Mhz
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assert CLK_FREQUENCY = 100000000;
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => RESET_LOW,
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PLL_RESET_BITS => 18,
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SOC_RESET_BITS => 1
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => system_clk_locked,
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ext_rst_in => ext_rst_n,
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pll_rst_out => pll_rst,
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rst_out => rst_gen_rst
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);
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-- Generate SoC reset
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soc_rst_gen: process(system_clk)
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begin
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if ext_rst_n = '0' then
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soc_rst <= '1';
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elsif rising_edge(system_clk) then
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soc_rst <= dram_sys_rst or not system_clk_locked;
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end if;
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end process;
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ddram_clk_p_vec <= (others => ddram_clk_p);
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ddram_clk_n_vec <= (others => ddram_clk_n);
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dram: entity work.litedram_wrapper
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generic map(
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DRAM_ABITS => 24,
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DRAM_ALINES => 14,
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DRAM_DLINES => 16,
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DRAM_CKLINES => 1,
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DRAM_PORT_WIDTH => 128,
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PAYLOAD_FILE => RAM_INIT_FILE,
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PAYLOAD_SIZE => PAYLOAD_SIZE
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)
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port map(
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clk_in => ext_clk,
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rst => pll_rst,
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system_clk => system_clk,
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system_reset => dram_sys_rst,
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pll_locked => system_clk_locked,
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wb_in => wb_dram_in,
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wb_out => wb_dram_out,
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wb_ctrl_in => wb_ext_io_in,
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wb_ctrl_out => wb_dram_ctrl_out,
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wb_ctrl_is_csr => wb_ext_is_dram_csr,
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wb_ctrl_is_init => wb_ext_is_dram_init,
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init_done => dram_init_done,
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init_error => dram_init_error,
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ddram_a => ddram_a,
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ddram_ba => ddram_ba,
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ddram_ras_n => ddram_ras_n,
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ddram_cas_n => ddram_cas_n,
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ddram_we_n => ddram_we_n,
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ddram_cs_n => open,
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ddram_dm => ddram_dm,
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ddram_dq => ddram_dq,
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ddram_dqs_p => ddram_dqs_p,
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ddram_dqs_n => ddram_dqs_n,
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ddram_clk_p => ddram_clk_p_vec,
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ddram_clk_n => ddram_clk_n_vec,
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ddram_cke => ddram_cke,
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ddram_odt => ddram_odt,
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ddram_reset_n => ddram_reset_n
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);
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end generate;
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has_liteeth : if USE_LITEETH generate
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component liteeth_core port (
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sys_clock : in std_ulogic;
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sys_reset : in std_ulogic;
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gmii_clocks_tx : in std_ulogic;
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gmii_clocks_gtx : out std_ulogic;
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gmii_clocks_rx : in std_ulogic;
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gmii_rst_n : out std_ulogic;
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gmii_mdio : inout std_ulogic;
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gmii_mdc : out std_ulogic;
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gmii_rx_dv : in std_ulogic;
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gmii_rx_er : in std_ulogic;
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gmii_rx_data : in std_ulogic_vector(7 downto 0);
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gmii_tx_en : out std_ulogic;
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gmii_tx_er : out std_ulogic;
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gmii_tx_data : out std_ulogic_vector(7 downto 0);
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gmii_col : in std_ulogic;
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gmii_crs : in std_ulogic;
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wishbone_adr : in std_ulogic_vector(29 downto 0);
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wishbone_dat_w : in std_ulogic_vector(31 downto 0);
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wishbone_dat_r : out std_ulogic_vector(31 downto 0);
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wishbone_sel : in std_ulogic_vector(3 downto 0);
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wishbone_cyc : in std_ulogic;
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wishbone_stb : in std_ulogic;
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wishbone_ack : out std_ulogic;
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wishbone_we : in std_ulogic;
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wishbone_cti : in std_ulogic_vector(2 downto 0);
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wishbone_bte : in std_ulogic_vector(1 downto 0);
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wishbone_err : out std_ulogic;
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interrupt : out std_ulogic
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);
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end component;
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signal wb_eth_cyc : std_ulogic;
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signal wb_eth_adr : std_ulogic_vector(29 downto 0);
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-- Change this to use a PLL instead of a BUFR to generate the 25Mhz
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-- reference clock to the PHY.
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constant USE_PLL : boolean := false;
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begin
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liteeth : liteeth_core
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port map(
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sys_clock => system_clk,
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sys_reset => soc_rst,
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gmii_clocks_tx => eth_clocks_tx,
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gmii_clocks_gtx => eth_clocks_gtx,
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gmii_clocks_rx => eth_clocks_rx,
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gmii_rst_n => eth_rst_n,
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gmii_mdio => eth_mdio,
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gmii_mdc => eth_mdc,
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gmii_rx_dv => eth_rx_dv,
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gmii_rx_er => eth_rx_er,
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gmii_rx_data => eth_rx_data,
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gmii_tx_en => eth_tx_en,
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gmii_tx_er => eth_tx_er,
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gmii_tx_data => eth_tx_data,
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gmii_col => eth_col,
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gmii_crs => eth_crs,
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wishbone_adr => wb_eth_adr,
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wishbone_dat_w => wb_ext_io_in.dat,
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wishbone_dat_r => wb_eth_out.dat,
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wishbone_sel => wb_ext_io_in.sel,
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wishbone_cyc => wb_eth_cyc,
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wishbone_stb => wb_ext_io_in.stb,
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wishbone_ack => wb_eth_out.ack,
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wishbone_we => wb_ext_io_in.we,
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wishbone_cti => "000",
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wishbone_bte => "00",
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wishbone_err => open,
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interrupt => ext_irq_eth
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);
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-- Gate cyc with "chip select" from soc
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wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth;
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-- Remove top address bits as liteeth decoder doesn't know about them
|
|
wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(14 downto 0);
|
|
|
|
-- LiteETH isn't pipelined
|
|
wb_eth_out.stall <= not wb_eth_out.ack;
|
|
|
|
end generate;
|
|
|
|
no_liteeth : if not USE_LITEETH generate
|
|
ext_irq_eth <= '0';
|
|
end generate;
|
|
|
|
-- SD card pmod
|
|
has_sdcard : if USE_LITESDCARD generate
|
|
component litesdcard_core port (
|
|
clk : in std_ulogic;
|
|
rst : in std_ulogic;
|
|
-- wishbone for accessing control registers
|
|
wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
|
|
wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
|
|
wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
|
|
wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
|
|
wb_ctrl_cyc : in std_ulogic;
|
|
wb_ctrl_stb : in std_ulogic;
|
|
wb_ctrl_ack : out std_ulogic;
|
|
wb_ctrl_we : in std_ulogic;
|
|
wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
|
|
wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
|
|
wb_ctrl_err : out std_ulogic;
|
|
-- wishbone for SD card core to use for DMA
|
|
wb_dma_adr : out std_ulogic_vector(29 downto 0);
|
|
wb_dma_dat_w : out std_ulogic_vector(31 downto 0);
|
|
wb_dma_dat_r : in std_ulogic_vector(31 downto 0);
|
|
wb_dma_sel : out std_ulogic_vector(3 downto 0);
|
|
wb_dma_cyc : out std_ulogic;
|
|
wb_dma_stb : out std_ulogic;
|
|
wb_dma_ack : in std_ulogic;
|
|
wb_dma_we : out std_ulogic;
|
|
wb_dma_cti : out std_ulogic_vector(2 downto 0);
|
|
wb_dma_bte : out std_ulogic_vector(1 downto 0);
|
|
wb_dma_err : in std_ulogic;
|
|
-- connections to SD card
|
|
sdcard_data : inout std_ulogic_vector(3 downto 0);
|
|
sdcard_cmd : inout std_ulogic;
|
|
sdcard_clk : out std_ulogic;
|
|
sdcard_cd : in std_ulogic;
|
|
irq : out std_ulogic
|
|
);
|
|
end component;
|
|
|
|
signal wb_sdcard_cyc : std_ulogic;
|
|
signal wb_sdcard_adr : std_ulogic_vector(29 downto 0);
|
|
|
|
begin
|
|
litesdcard : litesdcard_core
|
|
port map (
|
|
clk => system_clk,
|
|
rst => soc_rst,
|
|
wb_ctrl_adr => wb_sdcard_adr,
|
|
wb_ctrl_dat_w => wb_ext_io_in.dat,
|
|
wb_ctrl_dat_r => wb_sdcard_out.dat,
|
|
wb_ctrl_sel => wb_ext_io_in.sel,
|
|
wb_ctrl_cyc => wb_sdcard_cyc,
|
|
wb_ctrl_stb => wb_ext_io_in.stb,
|
|
wb_ctrl_ack => wb_sdcard_out.ack,
|
|
wb_ctrl_we => wb_ext_io_in.we,
|
|
wb_ctrl_cti => "000",
|
|
wb_ctrl_bte => "00",
|
|
wb_ctrl_err => open,
|
|
wb_dma_adr => wb_sddma_nr.adr,
|
|
wb_dma_dat_w => wb_sddma_nr.dat,
|
|
wb_dma_dat_r => wb_sddma_ir.dat,
|
|
wb_dma_sel => wb_sddma_nr.sel,
|
|
wb_dma_cyc => wb_sddma_nr.cyc,
|
|
wb_dma_stb => wb_sddma_nr.stb,
|
|
wb_dma_ack => wb_sddma_ir.ack,
|
|
wb_dma_we => wb_sddma_nr.we,
|
|
wb_dma_cti => open,
|
|
wb_dma_bte => open,
|
|
wb_dma_err => '0',
|
|
sdcard_data => sdcard_data,
|
|
sdcard_cmd => sdcard_cmd,
|
|
sdcard_clk => sdcard_clk,
|
|
sdcard_cd => sdcard_cd,
|
|
irq => ext_irq_sdcard
|
|
);
|
|
|
|
-- Gate cyc with chip select from SoC
|
|
wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard;
|
|
|
|
wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(13 downto 0);
|
|
|
|
wb_sdcard_out.stall <= not wb_sdcard_out.ack;
|
|
|
|
-- Convert non-pipelined DMA wishbone to pipelined by suppressing
|
|
-- non-acknowledged strobes
|
|
process(system_clk)
|
|
begin
|
|
if rising_edge(system_clk) then
|
|
wb_sddma_out <= wb_sddma_nr;
|
|
if wb_sddma_stb_sent = '1' or
|
|
(wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then
|
|
wb_sddma_out.stb <= '0';
|
|
end if;
|
|
if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then
|
|
wb_sddma_stb_sent <= '0';
|
|
elsif wb_sddma_in.stall = '0' then
|
|
wb_sddma_stb_sent <= wb_sddma_nr.stb;
|
|
end if;
|
|
wb_sddma_ir <= wb_sddma_in;
|
|
end if;
|
|
end process;
|
|
|
|
end generate;
|
|
|
|
-- Mux WB response on the IO bus
|
|
wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else
|
|
wb_sdcard_out when wb_ext_is_sdcard = '1' else
|
|
wb_dram_ctrl_out;
|
|
|
|
led0_n <= system_clk_locked;
|
|
led1_n <= not soc_rst;
|
|
|
|
end architecture behaviour;
|