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caravel-mpw7-20221125
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trace-test
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litedram-update
liteeth-update
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fpu-init
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caravel-mpw6-20220530
caravel-mpw5-20220323
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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microwatt/litedram/extras
History
Matt Johnston 4bd45af739 Move alt_reset to syscon 
Instead of connecting core_alt_reset to litedram init_done, it moves to
a syscon register bit. This simplifies top- files and future soc_reset
handling. sdram main.c can unset the alt_reset bit after sdram init.

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 		2 years ago
..
fusesoc-add-files.py litedram: Remove old "VexRiscV" based initializations 5 years ago
litedram-wrapper-l2.vhdl Move alt_reset to syscon 2 years ago
sim_dram_verilate.mk litedram: Add simulation support 5 years ago
sim_litedram.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 3 years ago
sim_litedram_c.cpp Fix build of core_dram_tb and dram_tb and fix tracing 2 years ago
wave.gtkw litedram: Add an L2 cache with store queue 5 years ago
wave.opt litedram: Add an L2 cache with store queue 5 years ago
wave_tb.gtkw litedram: l2: Latency improvements 4 years ago