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1003 lines
37 KiB
VHDL
1003 lines
37 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.insn_helpers.all;
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use work.helpers.all;
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-- 2 cycle LSU
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-- We calculate the address in the first cycle
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entity loadstore1 is
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generic (
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HAS_FPU : boolean := true;
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-- Non-zero to enable log data collection
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LOG_LENGTH : natural := 0
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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l_in : in Execute1ToLoadstore1Type;
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e_out : out Loadstore1ToExecute1Type;
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l_out : out Loadstore1ToWritebackType;
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d_out : out Loadstore1ToDcacheType;
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d_in : in DcacheToLoadstore1Type;
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m_out : out Loadstore1ToMmuType;
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m_in : in MmuToLoadstore1Type;
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dc_stall : in std_ulogic;
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events : out Loadstore1EventType;
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log_out : out std_ulogic_vector(9 downto 0)
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);
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end loadstore1;
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architecture behave of loadstore1 is
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-- State machine for unaligned loads/stores
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type state_t is (IDLE, -- ready for instruction
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MMU_WAIT -- waiting for MMU to finish doing something
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);
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type byte_index_t is array(0 to 7) of unsigned(2 downto 0);
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subtype byte_trim_t is std_ulogic_vector(1 downto 0);
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type trim_ctl_t is array(0 to 7) of byte_trim_t;
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type request_t is record
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valid : std_ulogic;
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dc_req : std_ulogic;
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load : std_ulogic;
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store : std_ulogic;
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tlbie : std_ulogic;
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dcbz : std_ulogic;
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read_spr : std_ulogic;
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write_spr : std_ulogic;
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mmu_op : std_ulogic;
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instr_fault : std_ulogic;
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do_update : std_ulogic;
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mode_32bit : std_ulogic;
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addr : std_ulogic_vector(63 downto 0);
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byte_sel : std_ulogic_vector(7 downto 0);
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second_bytes : std_ulogic_vector(7 downto 0);
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store_data : std_ulogic_vector(63 downto 0);
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instr_tag : instr_tag_t;
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write_reg : gspr_index_t;
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length : std_ulogic_vector(3 downto 0);
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elt_length : std_ulogic_vector(3 downto 0);
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byte_reverse : std_ulogic;
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brev_mask : unsigned(2 downto 0);
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sign_extend : std_ulogic;
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update : std_ulogic;
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xerc : xer_common_t;
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reserve : std_ulogic;
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atomic : std_ulogic;
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atomic_last : std_ulogic;
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rc : std_ulogic;
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nc : std_ulogic; -- non-cacheable access
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virt_mode : std_ulogic;
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priv_mode : std_ulogic;
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load_sp : std_ulogic;
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sprn : std_ulogic_vector(9 downto 0);
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is_slbia : std_ulogic;
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align_intr : std_ulogic;
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dword_index : std_ulogic;
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two_dwords : std_ulogic;
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incomplete : std_ulogic;
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nia : std_ulogic_vector(63 downto 0);
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end record;
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constant request_init : request_t := (valid => '0', dc_req => '0', load => '0', store => '0', tlbie => '0',
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dcbz => '0', read_spr => '0', write_spr => '0', mmu_op => '0',
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instr_fault => '0', do_update => '0',
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mode_32bit => '0', addr => (others => '0'),
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byte_sel => x"00", second_bytes => x"00",
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store_data => (others => '0'), instr_tag => instr_tag_init,
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write_reg => 7x"00", length => x"0",
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elt_length => x"0", byte_reverse => '0', brev_mask => "000",
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sign_extend => '0', update => '0',
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xerc => xerc_init, reserve => '0',
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atomic => '0', atomic_last => '0', rc => '0', nc => '0',
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virt_mode => '0', priv_mode => '0', load_sp => '0',
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sprn => 10x"0", is_slbia => '0', align_intr => '0',
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dword_index => '0', two_dwords => '0', incomplete => '0',
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nia => (others => '0'));
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type reg_stage1_t is record
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req : request_t;
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busy : std_ulogic;
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issued : std_ulogic;
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addr0 : std_ulogic_vector(63 downto 0);
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end record;
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type reg_stage2_t is record
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req : request_t;
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byte_index : byte_index_t;
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use_second : std_ulogic_vector(7 downto 0);
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busy : std_ulogic;
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wait_dc : std_ulogic;
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wait_mmu : std_ulogic;
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one_cycle : std_ulogic;
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wr_sel : std_ulogic_vector(1 downto 0);
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addr0 : std_ulogic_vector(63 downto 0);
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end record;
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type reg_stage3_t is record
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state : state_t;
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complete : std_ulogic;
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instr_tag : instr_tag_t;
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write_enable : std_ulogic;
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write_reg : gspr_index_t;
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write_data : std_ulogic_vector(63 downto 0);
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rc : std_ulogic;
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xerc : xer_common_t;
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store_done : std_ulogic;
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load_data : std_ulogic_vector(63 downto 0);
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dar : std_ulogic_vector(63 downto 0);
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dsisr : std_ulogic_vector(31 downto 0);
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ld_sp_data : std_ulogic_vector(31 downto 0);
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ld_sp_nz : std_ulogic;
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ld_sp_lz : std_ulogic_vector(5 downto 0);
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stage1_en : std_ulogic;
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interrupt : std_ulogic;
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intr_vec : integer range 0 to 16#fff#;
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nia : std_ulogic_vector(63 downto 0);
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srr1 : std_ulogic_vector(15 downto 0);
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events : Loadstore1EventType;
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end record;
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signal req_in : request_t;
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signal r1, r1in : reg_stage1_t;
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signal r2, r2in : reg_stage2_t;
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signal r3, r3in : reg_stage3_t;
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signal flush : std_ulogic;
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signal busy : std_ulogic;
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signal complete : std_ulogic;
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signal flushing : std_ulogic;
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signal store_sp_data : std_ulogic_vector(31 downto 0);
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signal load_dp_data : std_ulogic_vector(63 downto 0);
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signal store_data : std_ulogic_vector(63 downto 0);
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signal stage1_req : request_t;
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signal stage1_dcreq : std_ulogic;
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signal stage1_dreq : std_ulogic;
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-- Generate byte enables from sizes
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function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
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begin
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case length is
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when "0001" =>
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return "00000001";
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when "0010" =>
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return "00000011";
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when "0100" =>
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return "00001111";
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when "1000" =>
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return "11111111";
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when others =>
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return "00000000";
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end case;
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end function length_to_sel;
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-- Calculate byte enables
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-- This returns 16 bits, giving the select signals for two transfers,
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-- to account for unaligned loads or stores
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function xfer_data_sel(size : in std_logic_vector(3 downto 0);
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address : in std_logic_vector(2 downto 0))
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return std_ulogic_vector is
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variable longsel : std_ulogic_vector(15 downto 0);
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begin
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longsel := "00000000" & length_to_sel(size);
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return std_ulogic_vector(shift_left(unsigned(longsel),
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to_integer(unsigned(address))));
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end function xfer_data_sel;
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-- 23-bit right shifter for DP -> SP float conversions
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function shifter_23r(frac: std_ulogic_vector(22 downto 0); shift: unsigned(4 downto 0))
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return std_ulogic_vector is
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variable fs1 : std_ulogic_vector(22 downto 0);
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variable fs2 : std_ulogic_vector(22 downto 0);
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begin
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case shift(1 downto 0) is
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when "00" =>
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fs1 := frac;
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when "01" =>
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fs1 := '0' & frac(22 downto 1);
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when "10" =>
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fs1 := "00" & frac(22 downto 2);
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when others =>
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fs1 := "000" & frac(22 downto 3);
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end case;
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case shift(4 downto 2) is
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when "000" =>
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fs2 := fs1;
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when "001" =>
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fs2 := x"0" & fs1(22 downto 4);
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when "010" =>
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fs2 := x"00" & fs1(22 downto 8);
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when "011" =>
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fs2 := x"000" & fs1(22 downto 12);
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when "100" =>
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fs2 := x"0000" & fs1(22 downto 16);
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when others =>
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fs2 := x"00000" & fs1(22 downto 20);
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end case;
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return fs2;
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end;
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-- 23-bit left shifter for SP -> DP float conversions
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function shifter_23l(frac: std_ulogic_vector(22 downto 0); shift: unsigned(4 downto 0))
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return std_ulogic_vector is
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variable fs1 : std_ulogic_vector(22 downto 0);
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variable fs2 : std_ulogic_vector(22 downto 0);
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begin
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case shift(1 downto 0) is
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when "00" =>
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fs1 := frac;
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when "01" =>
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fs1 := frac(21 downto 0) & '0';
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when "10" =>
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fs1 := frac(20 downto 0) & "00";
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when others =>
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fs1 := frac(19 downto 0) & "000";
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end case;
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case shift(4 downto 2) is
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when "000" =>
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fs2 := fs1;
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when "001" =>
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fs2 := fs1(18 downto 0) & x"0" ;
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when "010" =>
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fs2 := fs1(14 downto 0) & x"00";
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when "011" =>
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fs2 := fs1(10 downto 0) & x"000";
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when "100" =>
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fs2 := fs1(6 downto 0) & x"0000";
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when others =>
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fs2 := fs1(2 downto 0) & x"00000";
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end case;
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return fs2;
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end;
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begin
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loadstore1_reg: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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r1.busy <= '0';
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r1.issued <= '0';
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r1.req.valid <= '0';
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r1.req.dc_req <= '0';
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r1.req.incomplete <= '0';
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r1.req.tlbie <= '0';
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r1.req.is_slbia <= '0';
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r1.req.instr_fault <= '0';
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r1.req.load <= '0';
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r1.req.priv_mode <= '0';
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r1.req.sprn <= (others => '0');
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r1.req.xerc <= xerc_init;
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r2.req.valid <= '0';
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r2.busy <= '0';
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r2.req.tlbie <= '0';
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r2.req.is_slbia <= '0';
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r2.req.instr_fault <= '0';
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r2.req.load <= '0';
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r2.req.priv_mode <= '0';
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r2.req.sprn <= (others => '0');
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r2.req.xerc <= xerc_init;
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r2.wait_dc <= '0';
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r2.wait_mmu <= '0';
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r2.one_cycle <= '0';
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r3.dar <= (others => '0');
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r3.dsisr <= (others => '0');
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r3.state <= IDLE;
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r3.write_enable <= '0';
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r3.interrupt <= '0';
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r3.complete <= '0';
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r3.stage1_en <= '1';
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r3.events.load_complete <= '0';
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r3.events.store_complete <= '0';
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flushing <= '0';
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else
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r1 <= r1in;
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r2 <= r2in;
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r3 <= r3in;
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flushing <= (flushing or (r1in.req.valid and r1in.req.align_intr)) and
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not flush;
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end if;
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stage1_dreq <= stage1_dcreq;
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if d_in.valid = '1' then
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assert r2.req.valid = '1' and r2.req.dc_req = '1' and r3.state = IDLE severity failure;
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end if;
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if d_in.error = '1' then
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assert r2.req.valid = '1' and r2.req.dc_req = '1' and r3.state = IDLE severity failure;
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end if;
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if m_in.done = '1' or m_in.err = '1' then
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assert r2.req.valid = '1' and r3.state = MMU_WAIT severity failure;
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end if;
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end if;
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end process;
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ls_fp_conv: if HAS_FPU generate
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-- Convert DP data to SP for stfs
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dp_to_sp: process(all)
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variable exp : unsigned(10 downto 0);
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variable frac : std_ulogic_vector(22 downto 0);
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variable shift : unsigned(4 downto 0);
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begin
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store_sp_data(31) <= l_in.data(63);
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store_sp_data(30 downto 0) <= (others => '0');
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exp := unsigned(l_in.data(62 downto 52));
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if exp > 896 then
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store_sp_data(30) <= l_in.data(62);
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store_sp_data(29 downto 0) <= l_in.data(58 downto 29);
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elsif exp >= 874 then
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-- denormalization required
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frac := '1' & l_in.data(51 downto 30);
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shift := 0 - exp(4 downto 0);
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store_sp_data(22 downto 0) <= shifter_23r(frac, shift);
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end if;
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end process;
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-- Convert SP data to DP for lfs
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sp_to_dp: process(all)
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variable exp : unsigned(7 downto 0);
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variable exp_dp : unsigned(10 downto 0);
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variable exp_nz : std_ulogic;
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variable exp_ao : std_ulogic;
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variable frac : std_ulogic_vector(22 downto 0);
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variable frac_shift : unsigned(4 downto 0);
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begin
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frac := r3.ld_sp_data(22 downto 0);
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exp := unsigned(r3.ld_sp_data(30 downto 23));
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exp_nz := or (r3.ld_sp_data(30 downto 23));
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exp_ao := and (r3.ld_sp_data(30 downto 23));
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frac_shift := (others => '0');
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if exp_ao = '1' then
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exp_dp := to_unsigned(2047, 11); -- infinity or NaN
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elsif exp_nz = '1' then
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exp_dp := 896 + resize(exp, 11); -- finite normalized value
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elsif r3.ld_sp_nz = '0' then
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exp_dp := to_unsigned(0, 11); -- zero
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else
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-- denormalized SP operand, need to normalize
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exp_dp := 896 - resize(unsigned(r3.ld_sp_lz), 11);
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frac_shift := unsigned(r3.ld_sp_lz(4 downto 0)) + 1;
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end if;
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load_dp_data(63) <= r3.ld_sp_data(31);
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load_dp_data(62 downto 52) <= std_ulogic_vector(exp_dp);
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load_dp_data(51 downto 29) <= shifter_23l(frac, frac_shift);
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load_dp_data(28 downto 0) <= (others => '0');
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end process;
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end generate;
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-- Translate a load/store instruction into the internal request format
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-- XXX this should only depend on l_in, but actually depends on
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-- r1.addr0 as well (in the l_in.second = 1 case).
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loadstore1_in: process(all)
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variable v : request_t;
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variable lsu_sum : std_ulogic_vector(63 downto 0);
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variable brev_lenm1 : unsigned(2 downto 0);
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variable long_sel : std_ulogic_vector(15 downto 0);
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variable addr : std_ulogic_vector(63 downto 0);
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variable sprn : std_ulogic_vector(9 downto 0);
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variable misaligned : std_ulogic;
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variable addr_mask : std_ulogic_vector(2 downto 0);
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begin
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v := request_init;
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sprn := std_ulogic_vector(to_unsigned(decode_spr_num(l_in.insn), 10));
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v.valid := l_in.valid;
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v.instr_tag := l_in.instr_tag;
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v.mode_32bit := l_in.mode_32bit;
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v.write_reg := l_in.write_reg;
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v.length := l_in.length;
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v.elt_length := l_in.length;
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v.byte_reverse := l_in.byte_reverse;
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v.sign_extend := l_in.sign_extend;
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v.update := l_in.update;
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v.xerc := l_in.xerc;
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v.reserve := l_in.reserve;
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v.rc := l_in.rc;
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v.nc := l_in.ci;
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v.virt_mode := l_in.virt_mode;
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v.priv_mode := l_in.priv_mode;
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v.sprn := sprn;
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v.nia := l_in.nia;
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lsu_sum := std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2));
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if HAS_FPU and l_in.is_32bit = '1' then
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v.store_data := x"00000000" & store_sp_data;
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else
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v.store_data := l_in.data;
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end if;
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addr := lsu_sum;
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if l_in.second = '1' then
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if l_in.update = '0' then
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-- for the second half of a 16-byte transfer,
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-- use the previous address plus 8.
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addr := std_ulogic_vector(unsigned(r1.addr0(63 downto 3)) + 1) & r1.addr0(2 downto 0);
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else
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-- for an update-form load, use the previous address
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-- as the value to write back to RA.
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addr := r1.addr0;
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end if;
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end if;
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if l_in.mode_32bit = '1' then
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addr(63 downto 32) := (others => '0');
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end if;
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v.addr := addr;
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-- XXX Temporary hack. Mark the op as non-cachable if the address
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-- is the form 0xc------- for a real-mode access.
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if addr(31 downto 28) = "1100" and l_in.virt_mode = '0' then
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v.nc := '1';
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end if;
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addr_mask := std_ulogic_vector(unsigned(l_in.length(2 downto 0)) - 1);
|
|
|
|
-- Do length_to_sel and work out if we are doing 2 dwords
|
|
long_sel := xfer_data_sel(v.length, addr(2 downto 0));
|
|
v.byte_sel := long_sel(7 downto 0);
|
|
v.second_bytes := long_sel(15 downto 8);
|
|
if long_sel(15 downto 8) /= "00000000" then
|
|
v.two_dwords := '1';
|
|
end if;
|
|
|
|
-- check alignment for larx/stcx
|
|
misaligned := or (addr_mask and addr(2 downto 0));
|
|
v.align_intr := l_in.reserve and misaligned;
|
|
|
|
v.atomic := not misaligned;
|
|
v.atomic_last := not misaligned and (l_in.second or not l_in.repeat);
|
|
|
|
case l_in.op is
|
|
when OP_STORE =>
|
|
v.store := '1';
|
|
when OP_LOAD =>
|
|
if l_in.update = '0' or l_in.second = '0' then
|
|
v.load := '1';
|
|
if HAS_FPU and l_in.is_32bit = '1' then
|
|
-- Allow an extra cycle for SP->DP precision conversion
|
|
v.load_sp := '1';
|
|
end if;
|
|
else
|
|
-- write back address to RA
|
|
v.do_update := '1';
|
|
end if;
|
|
when OP_DCBZ =>
|
|
v.dcbz := '1';
|
|
v.align_intr := v.nc;
|
|
when OP_TLBIE =>
|
|
v.tlbie := '1';
|
|
v.addr := l_in.addr2; -- address from RB for tlbie
|
|
v.is_slbia := l_in.insn(7);
|
|
v.mmu_op := '1';
|
|
when OP_MFSPR =>
|
|
v.read_spr := '1';
|
|
when OP_MTSPR =>
|
|
v.write_spr := '1';
|
|
v.mmu_op := sprn(8) or sprn(5);
|
|
when OP_FETCH_FAILED =>
|
|
-- send it to the MMU to do the radix walk
|
|
v.instr_fault := '1';
|
|
v.addr := l_in.nia;
|
|
v.mmu_op := '1';
|
|
when others =>
|
|
end case;
|
|
v.dc_req := l_in.valid and (v.load or v.store or v.dcbz) and not v.align_intr;
|
|
v.incomplete := v.dc_req and v.two_dwords;
|
|
|
|
-- Work out controls for load and store formatting
|
|
brev_lenm1 := "000";
|
|
if v.byte_reverse = '1' then
|
|
brev_lenm1 := unsigned(v.length(2 downto 0)) - 1;
|
|
end if;
|
|
v.brev_mask := brev_lenm1;
|
|
|
|
req_in <= v;
|
|
end process;
|
|
|
|
busy <= dc_stall or d_in.error or r1.busy or r2.busy;
|
|
complete <= r2.one_cycle or (r2.wait_dc and d_in.valid) or r3.complete;
|
|
|
|
-- Processing done in the first cycle of a load/store instruction
|
|
loadstore1_1: process(all)
|
|
variable v : reg_stage1_t;
|
|
variable req : request_t;
|
|
variable dcreq : std_ulogic;
|
|
variable issue : std_ulogic;
|
|
begin
|
|
v := r1;
|
|
issue := '0';
|
|
dcreq := '0';
|
|
|
|
if r1.busy = '0' then
|
|
req := req_in;
|
|
req.valid := l_in.valid;
|
|
if flushing = '1' then
|
|
-- Make this a no-op request rather than simply invalid.
|
|
-- It will never get to stage 3 since there is a request ahead of
|
|
-- it with align_intr = 1.
|
|
req.dc_req := '0';
|
|
end if;
|
|
issue := l_in.valid and req.dc_req;
|
|
if l_in.valid = '1' then
|
|
v.addr0 := req.addr;
|
|
end if;
|
|
else
|
|
req := r1.req;
|
|
if r1.req.dc_req = '1' and r1.issued = '0' then
|
|
issue := '1';
|
|
elsif r1.req.incomplete = '1' then
|
|
-- construct the second request for a misaligned access
|
|
req.dword_index := '1';
|
|
req.incomplete := '0';
|
|
req.addr := std_ulogic_vector(unsigned(r1.req.addr(63 downto 3)) + 1) & "000";
|
|
if r1.req.mode_32bit = '1' then
|
|
req.addr(32) := '0';
|
|
end if;
|
|
req.byte_sel := r1.req.second_bytes;
|
|
issue := '1';
|
|
else
|
|
-- For the lfs conversion cycle, leave the request valid
|
|
-- for another cycle but with req.dc_req = 0.
|
|
-- For an MMU request last cycle, we have nothing
|
|
-- to do in this cycle, so make it invalid.
|
|
if r1.req.load_sp = '0' then
|
|
req.valid := '0';
|
|
end if;
|
|
req.dc_req := '0';
|
|
end if;
|
|
end if;
|
|
|
|
if flush = '1' then
|
|
v.req.valid := '0';
|
|
v.req.dc_req := '0';
|
|
v.req.incomplete := '0';
|
|
v.issued := '0';
|
|
v.busy := '0';
|
|
elsif (dc_stall or d_in.error or r2.busy) = '0' then
|
|
-- we can change what's in r1 next cycle because the current thing
|
|
-- in r1 will go into r2
|
|
v.req := req;
|
|
dcreq := issue;
|
|
v.issued := issue;
|
|
v.busy := (issue and (req.incomplete or req.load_sp)) or (req.valid and req.mmu_op);
|
|
else
|
|
-- pipeline is stalled
|
|
if r1.issued = '1' and d_in.error = '1' then
|
|
v.issued := '0';
|
|
v.busy := '1';
|
|
end if;
|
|
end if;
|
|
|
|
stage1_req <= req;
|
|
stage1_dcreq <= dcreq;
|
|
r1in <= v;
|
|
end process;
|
|
|
|
-- Processing done in the second cycle of a load/store instruction.
|
|
-- Store data is formatted here and sent to the dcache.
|
|
-- The request in r1 is sent to stage 3 if stage 3 will not be busy next cycle.
|
|
loadstore1_2: process(all)
|
|
variable v : reg_stage2_t;
|
|
variable j : integer;
|
|
variable k : unsigned(2 downto 0);
|
|
variable kk : unsigned(3 downto 0);
|
|
variable idx : unsigned(2 downto 0);
|
|
variable byte_offset : unsigned(2 downto 0);
|
|
variable interrupt : std_ulogic;
|
|
begin
|
|
v := r2;
|
|
|
|
-- Byte reversing and rotating for stores.
|
|
-- Done in the second cycle (the cycle after l_in.valid = 1).
|
|
byte_offset := unsigned(r1.addr0(2 downto 0));
|
|
for i in 0 to 7 loop
|
|
k := (to_unsigned(i, 3) - byte_offset) xor r1.req.brev_mask;
|
|
j := to_integer(k) * 8;
|
|
store_data(i * 8 + 7 downto i * 8) <= r1.req.store_data(j + 7 downto j);
|
|
end loop;
|
|
|
|
if (dc_stall or d_in.error or r2.busy or l_in.e2stall) = '0' then
|
|
if r1.req.valid = '0' or r1.issued = '1' or r1.req.dc_req = '0' then
|
|
v.req := r1.req;
|
|
v.addr0 := r1.addr0;
|
|
v.req.store_data := store_data;
|
|
v.wait_dc := r1.req.valid and r1.req.dc_req and not r1.req.load_sp and
|
|
not r1.req.incomplete;
|
|
v.wait_mmu := r1.req.valid and r1.req.mmu_op;
|
|
v.busy := r1.req.valid and r1.req.mmu_op;
|
|
v.one_cycle := r1.req.valid and not (r1.req.dc_req or r1.req.mmu_op);
|
|
if r1.req.read_spr = '1' then
|
|
v.wr_sel := "00";
|
|
elsif r1.req.do_update = '1' or r1.req.store = '1' then
|
|
v.wr_sel := "01";
|
|
elsif r1.req.load_sp = '1' then
|
|
v.wr_sel := "10";
|
|
else
|
|
v.wr_sel := "11";
|
|
end if;
|
|
|
|
-- Work out load formatter controls for next cycle
|
|
for i in 0 to 7 loop
|
|
idx := to_unsigned(i, 3) xor r1.req.brev_mask;
|
|
kk := ('0' & idx) + ('0' & byte_offset);
|
|
v.use_second(i) := kk(3);
|
|
v.byte_index(i) := kk(2 downto 0);
|
|
end loop;
|
|
else
|
|
v.req.valid := '0';
|
|
v.wait_dc := '0';
|
|
v.wait_mmu := '0';
|
|
v.one_cycle := '0';
|
|
end if;
|
|
end if;
|
|
if r2.wait_mmu = '1' and m_in.done = '1' then
|
|
if r2.req.mmu_op = '1' then
|
|
v.req.valid := '0';
|
|
v.busy := '0';
|
|
end if;
|
|
v.wait_mmu := '0';
|
|
end if;
|
|
if r2.busy = '1' and r2.wait_mmu = '0' then
|
|
v.busy := '0';
|
|
end if;
|
|
|
|
interrupt := (r2.req.valid and r2.req.align_intr) or
|
|
(d_in.error and d_in.cache_paradox) or m_in.err;
|
|
if interrupt = '1' then
|
|
v.req.valid := '0';
|
|
v.busy := '0';
|
|
v.wait_dc := '0';
|
|
v.wait_mmu := '0';
|
|
elsif d_in.error = '1' then
|
|
v.wait_mmu := '1';
|
|
v.busy := '1';
|
|
end if;
|
|
|
|
r2in <= v;
|
|
end process;
|
|
|
|
-- Processing done in the third cycle of a load/store instruction.
|
|
-- At this stage we can do things that have side effects without
|
|
-- fear of the instruction getting flushed. This is the point at
|
|
-- which requests get sent to the MMU.
|
|
loadstore1_3: process(all)
|
|
variable v : reg_stage3_t;
|
|
variable j : integer;
|
|
variable req : std_ulogic;
|
|
variable mmureq : std_ulogic;
|
|
variable mmu_mtspr : std_ulogic;
|
|
variable write_enable : std_ulogic;
|
|
variable write_data : std_ulogic_vector(63 downto 0);
|
|
variable do_update : std_ulogic;
|
|
variable done : std_ulogic;
|
|
variable exception : std_ulogic;
|
|
variable data_permuted : std_ulogic_vector(63 downto 0);
|
|
variable data_trimmed : std_ulogic_vector(63 downto 0);
|
|
variable sprval : std_ulogic_vector(63 downto 0);
|
|
variable negative : std_ulogic;
|
|
variable dsisr : std_ulogic_vector(31 downto 0);
|
|
variable itlb_fault : std_ulogic;
|
|
variable trim_ctl : trim_ctl_t;
|
|
begin
|
|
v := r3;
|
|
|
|
req := '0';
|
|
mmureq := '0';
|
|
mmu_mtspr := '0';
|
|
done := '0';
|
|
exception := '0';
|
|
dsisr := (others => '0');
|
|
write_enable := '0';
|
|
sprval := (others => '0');
|
|
do_update := '0';
|
|
v.complete := '0';
|
|
v.srr1 := (others => '0');
|
|
v.events := (others => '0');
|
|
|
|
-- load data formatting
|
|
-- shift and byte-reverse data bytes
|
|
for i in 0 to 7 loop
|
|
j := to_integer(r2.byte_index(i)) * 8;
|
|
data_permuted(i * 8 + 7 downto i * 8) := d_in.data(j + 7 downto j);
|
|
end loop;
|
|
|
|
-- Work out the sign bit for sign extension.
|
|
-- For unaligned loads crossing two dwords, the sign bit is in the
|
|
-- first dword for big-endian (byte_reverse = 1), or the second dword
|
|
-- for little-endian.
|
|
if r2.req.dword_index = '1' and r2.req.byte_reverse = '1' then
|
|
negative := (r2.req.length(3) and r3.load_data(63)) or
|
|
(r2.req.length(2) and r3.load_data(31)) or
|
|
(r2.req.length(1) and r3.load_data(15)) or
|
|
(r2.req.length(0) and r3.load_data(7));
|
|
else
|
|
negative := (r2.req.length(3) and data_permuted(63)) or
|
|
(r2.req.length(2) and data_permuted(31)) or
|
|
(r2.req.length(1) and data_permuted(15)) or
|
|
(r2.req.length(0) and data_permuted(7));
|
|
end if;
|
|
|
|
-- trim and sign-extend
|
|
for i in 0 to 7 loop
|
|
if i < to_integer(unsigned(r2.req.length)) then
|
|
if r2.req.dword_index = '1' then
|
|
trim_ctl(i) := '1' & not r2.use_second(i);
|
|
else
|
|
trim_ctl(i) := "10";
|
|
end if;
|
|
else
|
|
trim_ctl(i) := "00";
|
|
end if;
|
|
end loop;
|
|
|
|
for i in 0 to 7 loop
|
|
case trim_ctl(i) is
|
|
when "11" =>
|
|
data_trimmed(i * 8 + 7 downto i * 8) := r3.load_data(i * 8 + 7 downto i * 8);
|
|
when "10" =>
|
|
data_trimmed(i * 8 + 7 downto i * 8) := data_permuted(i * 8 + 7 downto i * 8);
|
|
when others =>
|
|
data_trimmed(i * 8 + 7 downto i * 8) := (others => negative and r2.req.sign_extend);
|
|
end case;
|
|
end loop;
|
|
|
|
if HAS_FPU then
|
|
-- Single-precision FP conversion for loads
|
|
v.ld_sp_data := data_trimmed(31 downto 0);
|
|
v.ld_sp_nz := or (data_trimmed(22 downto 0));
|
|
v.ld_sp_lz := count_left_zeroes(data_trimmed(22 downto 0));
|
|
end if;
|
|
|
|
if d_in.valid = '1' and r2.req.load = '1' then
|
|
v.load_data := data_permuted;
|
|
end if;
|
|
|
|
if r2.req.valid = '1' then
|
|
if r2.req.read_spr = '1' then
|
|
write_enable := '1';
|
|
-- partial decode on SPR number should be adequate given
|
|
-- the restricted set that get sent down this path
|
|
if r2.req.sprn(8) = '0' and r2.req.sprn(5) = '0' then
|
|
if r2.req.sprn(0) = '0' then
|
|
sprval := x"00000000" & r3.dsisr;
|
|
else
|
|
sprval := r3.dar;
|
|
end if;
|
|
else
|
|
-- reading one of the SPRs in the MMU
|
|
sprval := m_in.sprval;
|
|
end if;
|
|
end if;
|
|
if r2.req.align_intr = '1' then
|
|
-- generate alignment interrupt
|
|
exception := '1';
|
|
end if;
|
|
if r2.req.do_update = '1' then
|
|
do_update := '1';
|
|
end if;
|
|
if r2.req.load_sp = '1' and r2.req.dc_req = '0' then
|
|
write_enable := '1';
|
|
end if;
|
|
if r2.req.write_spr = '1' and r2.req.mmu_op = '0' then
|
|
if r2.req.sprn(0) = '0' then
|
|
v.dsisr := r2.req.store_data(31 downto 0);
|
|
else
|
|
v.dar := r2.req.store_data;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
|
|
if r3.state = IDLE and r2.req.valid = '1' and r2.req.mmu_op = '1' then
|
|
-- send request (tlbie, mtspr, itlb miss) to MMU
|
|
mmureq := not r2.req.write_spr;
|
|
mmu_mtspr := r2.req.write_spr;
|
|
if r2.req.instr_fault = '1' then
|
|
v.events.itlb_miss := '1';
|
|
end if;
|
|
v.state := MMU_WAIT;
|
|
end if;
|
|
|
|
if d_in.valid = '1' then
|
|
if r2.req.incomplete = '0' then
|
|
write_enable := r2.req.load and not r2.req.load_sp;
|
|
-- stores write back rA update
|
|
do_update := r2.req.update and r2.req.store;
|
|
end if;
|
|
end if;
|
|
if d_in.error = '1' then
|
|
if d_in.cache_paradox = '1' then
|
|
-- signal an interrupt straight away
|
|
exception := '1';
|
|
dsisr(63 - 38) := not r2.req.load;
|
|
-- XXX there is no architected bit for this
|
|
-- (probably should be a machine check in fact)
|
|
dsisr(63 - 35) := d_in.cache_paradox;
|
|
else
|
|
-- Look up the translation for TLB miss
|
|
-- and also for permission error and RC error
|
|
-- in case the PTE has been updated.
|
|
mmureq := '1';
|
|
v.state := MMU_WAIT;
|
|
v.stage1_en := '0';
|
|
end if;
|
|
end if;
|
|
|
|
if m_in.done = '1' then
|
|
if r2.req.dc_req = '1' then
|
|
-- retry the request now that the MMU has installed a TLB entry
|
|
req := '1';
|
|
else
|
|
v.complete := '1';
|
|
end if;
|
|
end if;
|
|
if m_in.err = '1' then
|
|
exception := '1';
|
|
dsisr(63 - 33) := m_in.invalid;
|
|
dsisr(63 - 36) := m_in.perm_error;
|
|
dsisr(63 - 38) := r2.req.store or r2.req.dcbz;
|
|
dsisr(63 - 44) := m_in.badtree;
|
|
dsisr(63 - 45) := m_in.rc_error;
|
|
end if;
|
|
|
|
if (m_in.done or m_in.err) = '1' then
|
|
v.stage1_en := '1';
|
|
v.state := IDLE;
|
|
end if;
|
|
|
|
v.events.load_complete := r2.req.load and complete;
|
|
v.events.store_complete := (r2.req.store or r2.req.dcbz) and complete;
|
|
|
|
-- generate DSI or DSegI for load/store exceptions
|
|
-- or ISI or ISegI for instruction fetch exceptions
|
|
v.interrupt := exception;
|
|
if exception = '1' then
|
|
v.nia := r2.req.nia;
|
|
if r2.req.align_intr = '1' then
|
|
v.intr_vec := 16#600#;
|
|
v.dar := r2.req.addr;
|
|
elsif r2.req.instr_fault = '0' then
|
|
v.dar := r2.req.addr;
|
|
if m_in.segerr = '0' then
|
|
v.intr_vec := 16#300#;
|
|
v.dsisr := dsisr;
|
|
else
|
|
v.intr_vec := 16#380#;
|
|
end if;
|
|
else
|
|
if m_in.segerr = '0' then
|
|
v.srr1(47 - 33) := m_in.invalid;
|
|
v.srr1(47 - 35) := m_in.perm_error; -- noexec fault
|
|
v.srr1(47 - 44) := m_in.badtree;
|
|
v.srr1(47 - 45) := m_in.rc_error;
|
|
v.intr_vec := 16#400#;
|
|
else
|
|
v.intr_vec := 16#480#;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
|
|
case r2.wr_sel is
|
|
when "00" =>
|
|
-- mfspr result
|
|
write_data := sprval;
|
|
when "01" =>
|
|
-- update reg
|
|
write_data := r2.addr0;
|
|
when "10" =>
|
|
-- lfs result
|
|
write_data := load_dp_data;
|
|
when others =>
|
|
-- load data
|
|
write_data := data_trimmed;
|
|
end case;
|
|
|
|
-- Update outputs to dcache
|
|
if r3.stage1_en = '1' then
|
|
d_out.valid <= stage1_dcreq;
|
|
d_out.load <= stage1_req.load;
|
|
d_out.dcbz <= stage1_req.dcbz;
|
|
d_out.nc <= stage1_req.nc;
|
|
d_out.reserve <= stage1_req.reserve;
|
|
d_out.atomic <= stage1_req.atomic;
|
|
d_out.atomic_last <= stage1_req.atomic_last;
|
|
d_out.addr <= stage1_req.addr;
|
|
d_out.byte_sel <= stage1_req.byte_sel;
|
|
d_out.virt_mode <= stage1_req.virt_mode;
|
|
d_out.priv_mode <= stage1_req.priv_mode;
|
|
else
|
|
d_out.valid <= req;
|
|
d_out.load <= r2.req.load;
|
|
d_out.dcbz <= r2.req.dcbz;
|
|
d_out.nc <= r2.req.nc;
|
|
d_out.reserve <= r2.req.reserve;
|
|
d_out.atomic <= r2.req.atomic;
|
|
d_out.atomic_last <= r2.req.atomic_last;
|
|
d_out.addr <= r2.req.addr;
|
|
d_out.byte_sel <= r2.req.byte_sel;
|
|
d_out.virt_mode <= r2.req.virt_mode;
|
|
d_out.priv_mode <= r2.req.priv_mode;
|
|
end if;
|
|
if stage1_dreq = '1' then
|
|
d_out.data <= store_data;
|
|
else
|
|
d_out.data <= r2.req.store_data;
|
|
end if;
|
|
d_out.hold <= l_in.e2stall;
|
|
|
|
-- Update outputs to MMU
|
|
m_out.valid <= mmureq;
|
|
m_out.iside <= r2.req.instr_fault;
|
|
m_out.load <= r2.req.load;
|
|
m_out.priv <= r2.req.priv_mode;
|
|
m_out.tlbie <= r2.req.tlbie;
|
|
m_out.mtspr <= mmu_mtspr;
|
|
m_out.sprn <= r2.req.sprn;
|
|
m_out.addr <= r2.req.addr;
|
|
m_out.slbia <= r2.req.is_slbia;
|
|
m_out.rs <= r2.req.store_data;
|
|
|
|
-- Update outputs to writeback
|
|
l_out.valid <= complete;
|
|
l_out.instr_tag <= r2.req.instr_tag;
|
|
l_out.write_enable <= write_enable or do_update;
|
|
l_out.write_reg <= r2.req.write_reg;
|
|
l_out.write_data <= write_data;
|
|
l_out.xerc <= r2.req.xerc;
|
|
l_out.rc <= r2.req.rc and complete;
|
|
l_out.store_done <= d_in.store_done;
|
|
l_out.interrupt <= r3.interrupt;
|
|
l_out.intr_vec <= r3.intr_vec;
|
|
l_out.srr0 <= r3.nia;
|
|
l_out.srr1 <= r3.srr1;
|
|
|
|
-- update busy signal back to execute1
|
|
e_out.busy <= busy;
|
|
e_out.l2stall <= dc_stall or d_in.error or r2.busy;
|
|
|
|
events <= r3.events;
|
|
|
|
flush <= exception;
|
|
|
|
-- Update registers
|
|
r3in <= v;
|
|
|
|
end process;
|
|
|
|
l1_log: if LOG_LENGTH > 0 generate
|
|
signal log_data : std_ulogic_vector(9 downto 0);
|
|
begin
|
|
ls1_log: process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
log_data <= e_out.busy &
|
|
l_out.interrupt &
|
|
l_out.valid &
|
|
m_out.valid &
|
|
d_out.valid &
|
|
m_in.done &
|
|
r2.req.dword_index &
|
|
r2.req.valid &
|
|
r2.wait_dc &
|
|
std_ulogic_vector(to_unsigned(state_t'pos(r3.state), 1));
|
|
end if;
|
|
end process;
|
|
log_out <= log_data;
|
|
end generate;
|
|
|
|
end;
|