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91 lines
2.1 KiB
C
91 lines
2.1 KiB
C
#include <unistd.h>
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#include <string.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdarg.h>
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#include <stdio.h>
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#include <generated/git.h>
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#include "microwatt_soc.h"
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#include "io.h"
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#include "sdram.h"
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#include "console.h"
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int _printf(const char *fmt, ...)
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{
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int count;
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char buffer[320];
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va_list ap;
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va_start(ap, fmt);
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count = vsnprintf(buffer, sizeof(buffer), fmt, ap);
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va_end(ap);
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puts(buffer);
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return count;
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}
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void flush_cpu_dcache(void)
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{
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}
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void flush_cpu_icache(void)
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{
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__asm__ volatile ("icbi 0,0; isync" : : : "memory");
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}
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void main(void)
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{
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unsigned long long ftr, val;
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/* Init the UART */
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potato_uart_init();
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printf("\n\nWelcome to Microwatt !\n\n");
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/* TODO: Add core version information somewhere in syscon, possibly
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* extracted from git
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*/
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printf(" Soc signature: %016llx\n",
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(unsigned long long)readq(SYSCON_BASE + SYS_REG_SIGNATURE));
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printf(" Soc features: ");
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ftr = readq(SYSCON_BASE + SYS_REG_INFO);
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if (ftr & SYS_REG_INFO_HAS_UART)
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printf("UART ");
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if (ftr & SYS_REG_INFO_HAS_DRAM)
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printf("DRAM ");
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if (ftr & SYS_REG_INFO_HAS_BRAM)
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printf("BRAM ");
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printf("\n");
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if (ftr & SYS_REG_INFO_HAS_BRAM) {
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val = readq(SYSCON_BASE + SYS_REG_BRAMINFO) & SYS_REG_BRAMINFO_SIZE_MASK;
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printf(" BRAM: %lld KB\n", val / 1024);
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}
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if (ftr & SYS_REG_INFO_HAS_DRAM) {
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val = readq(SYSCON_BASE + SYS_REG_DRAMINFO) & SYS_REG_DRAMINFO_SIZE_MASK;
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printf(" DRAM: %lld MB\n", val / (1024 * 1024));
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val = readq(SYSCON_BASE + SYS_REG_DRAMINITINFO);
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printf(" DRAM INIT: %lld KB\n", val / 1024);
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}
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val = readq(SYSCON_BASE + SYS_REG_CLKINFO) & SYS_REG_CLKINFO_FREQ_MASK;
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printf(" CLK: %lld MHz\n", val / 1000000);
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printf("\n");
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if (ftr & SYS_REG_INFO_HAS_DRAM) {
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printf("LiteDRAM built from Migen %s and LiteX %s\n",
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MIGEN_GIT_SHA1, LITEX_GIT_SHA1);
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sdrinit();
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}
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if (ftr & SYS_REG_INFO_HAS_BRAM)
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printf("Booting from BRAM...\n");
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else {
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void *s = (void *)(DRAM_INIT_BASE + 0x4000);
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void *d = (void *)DRAM_BASE;
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int sz = (0x10000 - 0x4000);
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printf("Copying payload to DRAM...\n");
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memcpy(d, s, sz);
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printf("Booting from DRAM...\n");
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flush_cpu_icache();
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}
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}
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