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Benjamin Herrenschmidt 573b6b4bc4 soc: Rework interconnect ... This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
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LICENSE	…
arty_a7.xdc	fpga: Hookup Arty to litedram	5 years ago
clk_gen_bypass.vhd	…
clk_gen_mcmm.vhd	…
clk_gen_plle2.vhd	…
cmod_a7-35.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
firmware.hex	…
hello_world.hex	hello_world: Use new headers and frequency from syscon	5 years ago
main_bram.vhdl	Fix some ghdlsynth issues with fpga_bram	5 years ago
nexys-video.xdc	fpga: Hookup nexys-video to litedram	5 years ago
nexys_a7.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
pp_fifo.vhd	pp_fifo: Fix full fifo losing all data on simultaneous push & pop	5 years ago
pp_soc_uart.vhd	pp_soc_uart: Fix rx synchronizers and ensure stable tx init state	5 years ago
pp_utilities.vhd	…
soc_reset.vhdl	soc_reset: Use counters, add synchronizers	5 years ago
soc_reset_tb.vhdl	Exit cleanly from testbench on success	5 years ago
top-arty.vhdl	soc: Rework interconnect	5 years ago
top-generic.vhdl	soc: Rework interconnect	5 years ago
top-nexys-video.vhdl	soc: Rework interconnect	5 years ago