cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity
You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'd7d7a3afd4'
${ noResults }
microwatt/scripts
History
Paul Mackerras 205c0e2c78 Implement the wait instruction 
This implements the behaviour of the 'wait 0' instruction of pausing
execution of instructions until an exception arises.  The exceptions
that terminate a wait are a pending trace exception, external
interrupt request, PMU interrupt request, or decrementer negative
exception.  These exception conditions terminate a wait even if not
enabled to generate an interrupt (e.g. if MSR[EE] is zero).

This is implemented by having execute1 assert its busy_out signal
while the wait state exists.  The wait state is set by the completion
of the wait instruction and cleared by a pending exception.

If the WC operand of the wait instruction is non-zero, indicating wait
for reservation loss or wait for a short period, then the wait
instruction does not wait, but just acts as a no-op.

In order to make space in the insn_type_t type without going over 64
elements, this combines OP_DCBT and OP_ICBT into a single OP_XCBT,
since they were both no-ops (except for their influence on how SRR1 is
set on a trace interrupt, where they were identical).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 		1 month ago
..
fmt_log Implement the wait instruction 1 month ago
mw_debug execute1: Make CFAR able to be written using mtspr and read using DMI debug 1 month ago
bin2hex.py bin2hex: Make sure to generate little endian files 5 years ago
dependencies.py uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 5 years ago
gen_icache_tb.py icache_tb: Improve test and include test file 5 years ago
make_version.sh syscon: Implement a register for storing git hash info 2 years ago
make_version_fusesoc.py syscon: Implement a register for storing git hash info 2 years ago
run_test.sh scripts/run_test: Use grep -E instead of egrep 1 year ago
run_test_console.sh test: Add test for metavalues 3 years ago
test_micropython.py Update micropython 5 years ago
test_micropython_long.py Update micropython 5 years ago
test_micropython_verilator.py makefile: Add some verilator micropython tests 3 years ago
test_micropython_verilator_long.py makefile: Add some verilator micropython tests 3 years ago
vhdltags Add VHDL TAGS 5 years ago