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64 lines
1.5 KiB
VHDL
64 lines
1.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity cr_hazard is
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generic (
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PIPELINE_DEPTH : natural := 2
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);
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port(
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clk : in std_logic;
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cr_read_in : in std_ulogic;
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cr_write_in : in std_ulogic;
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stall_out : out std_ulogic
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);
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end entity cr_hazard;
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architecture behaviour of cr_hazard is
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type pipeline_entry_type is record
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valid : std_ulogic;
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end record;
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constant pipeline_entry_init : pipeline_entry_type := (valid => '0');
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type pipeline_t is array(0 to PIPELINE_DEPTH-1) of pipeline_entry_type;
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constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
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signal r, rin : pipeline_t := pipeline_t_init;
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begin
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cr_hazard0: process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process;
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cr_hazard1: process(all)
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variable v : pipeline_t;
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begin
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v := r;
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stall_out <= '0';
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loop_0: for i in 0 to PIPELINE_DEPTH-1 loop
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if (r(i).valid = cr_read_in) then
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stall_out <= '1';
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end if;
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end loop;
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v(0).valid := cr_write_in;
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loop_1: for i in 0 to PIPELINE_DEPTH-2 loop
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-- propagate to next slot
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v(i+1) := r(i);
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end loop;
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-- asynchronous output
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if cr_read_in = '0' then
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stall_out <= '0';
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end if;
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-- update registers
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rin <= v;
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end process;
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end;
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