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103 lines
3.2 KiB
VHDL
103 lines
3.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.crhelpers.all;
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entity writeback is
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port (
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clk : in std_ulogic;
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e_in : in Execute1ToWritebackType;
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l_in : in Loadstore1ToWritebackType;
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w_out : out WritebackToRegisterFileType;
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c_out : out WritebackToCrFileType;
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complete_out : out std_ulogic
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);
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end entity writeback;
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architecture behaviour of writeback is
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begin
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writeback_1: process(all)
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variable x : std_ulogic_vector(0 downto 0);
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variable y : std_ulogic_vector(0 downto 0);
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variable w : std_ulogic_vector(0 downto 0);
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variable cf: std_ulogic_vector(3 downto 0);
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variable zero : std_ulogic;
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variable sign : std_ulogic;
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variable scf : std_ulogic_vector(3 downto 0);
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begin
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x(0) := e_in.valid;
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y(0) := l_in.valid;
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assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;
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x(0) := e_in.write_enable;
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y(0) := l_in.write_enable;
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assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;
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w(0) := e_in.write_cr_enable;
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x(0) := (e_in.write_enable and e_in.rc);
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assert (to_integer(unsigned(w)) + to_integer(unsigned(x))) <= 1 severity failure;
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w_out <= WritebackToRegisterFileInit;
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c_out <= WritebackToCrFileInit;
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complete_out <= '0';
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if e_in.valid = '1' or l_in.valid = '1' then
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complete_out <= '1';
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end if;
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if e_in.write_enable = '1' then
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w_out.write_reg <= e_in.write_reg;
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w_out.write_data <= e_in.write_data;
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w_out.write_enable <= '1';
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end if;
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if e_in.write_cr_enable = '1' then
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c_out.write_cr_enable <= '1';
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c_out.write_cr_mask <= e_in.write_cr_mask;
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c_out.write_cr_data <= e_in.write_cr_data;
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end if;
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if e_in.write_xerc_enable = '1' then
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c_out.write_xerc_enable <= '1';
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c_out.write_xerc_data <= e_in.xerc;
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end if;
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if l_in.write_enable = '1' then
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w_out.write_reg <= gpr_to_gspr(l_in.write_reg);
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w_out.write_data <= l_in.write_data;
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w_out.write_enable <= '1';
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end if;
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if l_in.rc = '1' then
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-- st*cx. instructions
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scf(3) := '0';
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scf(2) := '0';
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scf(1) := l_in.store_done;
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scf(0) := l_in.xerc.so;
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c_out.write_cr_enable <= '1';
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c_out.write_cr_mask <= num_to_fxm(0);
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c_out.write_cr_data(31 downto 28) <= scf;
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end if;
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-- Perform CR0 update for RC forms
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-- Note that loads never have a form with an RC bit, therefore this can test e_in.write_data
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if e_in.rc = '1' and e_in.write_enable = '1' then
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sign := e_in.write_data(63);
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zero := not (or e_in.write_data);
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c_out.write_cr_enable <= '1';
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c_out.write_cr_mask <= num_to_fxm(0);
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cf(3) := sign;
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cf(2) := not sign and not zero;
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cf(1) := zero;
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cf(0) := e_in.xerc.so;
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c_out.write_cr_data(31 downto 28) <= cf;
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end if;
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end process;
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end;
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