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microwatt/fpga
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Paul Mackerras 45cd8f4fc3 core: Add support for floating-point loads and stores 
This extends the register file so it can hold FPR values, and
implements the FP loads and stores that do not require conversion
between single and double precision.

We now have the FP, FE0 and FE1 bits in MSR.  FP loads and stores
cause a FP unavailable interrupt if MSR[FP] = 0.

The FPU facilities are optional and their presence is controlled by
the HAS_FPU generic passed down from the top-level board file.  It
defaults to true for all except the A7-35 boards.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
..
LICENSE Initial import of microwatt
acorn-cle-215.xdc acorn: Add support for the Acorn CLE 215+
arty_a7.xdc uart: Import and hook up opencore 16550 compatible UART
clk_gen_bypass.vhd Fix clk_gen_bypass
clk_gen_ecp5.vhd Add PLL for ECP5 device
clk_gen_mcmm.vhd Improve PLL/MMCM clocks configuration
clk_gen_plle2.vhd acorn: Add support for the Acorn CLE 215+
cmod_a7-35.xdc Add SPI configuration to Xilinx constraint files
firmware.hex Add a few more FPGA related files
fpga-random.vhdl Add random number generator and implement the darn instruction
fpga-random.xdc Add random number generator and implement the darn instruction
genesys2.xdc fpga: Add support for Genesys2
hello_world.hex hello_world: Use new headers and frequency from syscon
main_bram.vhdl Fix some ghdlsynth issues with fpga_bram
nexys-video.xdc spi: Add SPI Flash controller
nexys_a7.xdc Add SPI configuration to Xilinx constraint files
pp_fifo.vhd pp_fifo: Fix full fifo losing all data on simultaneous push & pop
pp_soc_uart.vhd uart: Remove combinational loops on ack and stall signal
pp_utilities.vhd Initial import of microwatt
soc_reset.vhdl soc_reset: Use counters, add synchronizers
soc_reset_tb.vhdl Exit cleanly from testbench on success
top-acorn-cle-215.vhdl acorn: Add support for the Acorn CLE 215+
top-arty.vhdl core: Add support for floating-point loads and stores
top-generic.vhdl core: Add support for floating-point loads and stores
top-genesys2.vhdl fpga: Add support for Genesys2
top-nexys-video.vhdl core: Add support for floating-point loads and stores