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power-fv/power_fv/insn/spec/compare.py

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In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
from amaranth import *
from power_fv import pfv
from power_fv.insn.const import *
from . import InsnSpec
from .utils import iea
__all__ = ["CompareSpec"]
class CompareSpec(InsnSpec, Elaboratable):
def __init__(self, insn):
self.pfv = pfv.Interface()
self.insn = insn
def elaborate(self, platform):
m = Module()
m.d.comb += [
self.pfv.stb .eq(1),
self.pfv.insn.eq(Cat(Const(0, 32), self.insn.as_value())),
self.pfv.intr.eq(0),
self.pfv.nia .eq(iea(self.pfv.cia + 4, self.pfv.msr.r_data.sf)),
self.pfv.msr.r_mask.sf.eq(1),
self.pfv.xer.r_mask.so.eq(1),
]
src_a = Signal(64)
src_b = Signal(64)
result = Record([
("lt", 1),
("gt", 1),
("eq_", 1),
("so", 1),
])
# Operand A : (RA) or [(RA)(32:63) sign-extended or zero-extended]
m.d.comb += [
self.pfv.ra.index.eq(self.insn.RA),
self.pfv.ra.r_stb.eq(1),
]
if isinstance(self.insn, (CMPI, CMP)):
with m.If(self.insn.L):
m.d.comb += src_a.eq(self.pfv.ra.r_data)
with m.Else():
m.d.comb += src_a.eq(self.pfv.ra.r_data[:32].as_signed())
elif isinstance(self.insn, (CMPL, CMPLI)):
with m.If(self.insn.L):
m.d.comb += src_a.eq(self.pfv.ra.r_data)
with m.Else():
m.d.comb += src_a.eq(self.pfv.ra.r_data[:32].as_unsigned())
else:
assert False
# Operand B : SI or UI or (RB) or [(RB)(32:63) sign-extended or zero-extended]
if isinstance(self.insn, (CMP, CMPL)):
m.d.comb += [
self.pfv.rb.index.eq(self.insn.RB),
self.pfv.rb.r_stb.eq(1),
]
if isinstance(self.insn, CMPI):
m.d.comb += src_b.eq(self.insn.SI)
elif isinstance(self.insn, CMPLI):
m.d.comb += src_b.eq(self.insn.UI)
elif isinstance(self.insn, CMP):
with m.If(self.insn.L):
m.d.comb += src_b.eq(self.pfv.rb.r_data)
with m.Else():
m.d.comb += src_b.eq(self.pfv.rb.r_data[:32].as_signed())
elif isinstance(self.insn, CMPL):
with m.If(self.insn.L):
m.d.comb += src_b.eq(self.pfv.rb.r_data)
with m.Else():
m.d.comb += src_b.eq(self.pfv.rb.r_data[:32].as_unsigned())
else:
assert False
# Result
if isinstance(self.insn, (CMPI, CMP)):
m.d.comb += result.lt.eq(src_a.as_signed() < src_b.as_signed())
elif isinstance(self.insn, (CMPLI, CMPL)):
m.d.comb += result.lt.eq(src_a.as_unsigned() < src_b.as_unsigned())
else:
assert False
m.d.comb += [
result.gt .eq(~(result.lt | result.eq_)),
result.eq_.eq(src_a == src_b),
result.so .eq(self.pfv.xer.r_data.so),
]
m.d.comb += [
self.pfv.cr.w_mask[::-1].word_select(self.insn.BF, width=4).eq(0b1111),
self.pfv.cr.w_data[::-1].word_select(self.insn.BF, width=4).eq(result),
]
return m