cores
/
power-fv
3
1
Fork 0
Code Issues 18 Pull Requests Projects Releases Wiki Activity
You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
dinofly
main
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '5ca0001b4b'
${ noResults }
power-fv/power_fv/insn/spec/cr.py

82 lines
2.7 KiB
Python
Raw Normal View History Unescape Escape

In-depth refactoring, improved user interface. * A PowerFVSession class provides a REPL interface. Functionality is split into commands (e.g. add checks, build) which can be provided interactively or from a file. See cores/microwatt for an example of its integration. * Instruction specifications are now separated from verification testbenches. An InsnSpec class provides a behavioral model using the same PowerFV interface as a core. This interface is output-only for a core, but bidirectional for the InsnSpec: - fields related to context (e.g. read data) are inputs, - fields related to side-effects (e.g. write strobes) are outputs. The testbench is responsible for driving inputs to the same values as the core, then check outputs for equivalence. This decoupling provides a path towards using PowerFV in simulation. * Instruction encodings are now defined by their fields, not their format (which was problematic e.g. X-form has dozens of variants). Field declarations can be preset to a value, or left undefined. In the latter case, they are implicitly cast to AnyConst (which is useful for arbitrary values like immediates).
2 years ago
from amaranth import *
from power_fv import pfv
from power_fv.insn.const import *
from . import InsnSpec
from .utils import iea
__all__ = ["CRSpec"]
class CRSpec(InsnSpec, Elaboratable):
def __init__(self, insn):
self.pfv = pfv.Interface()
self.insn = insn
def elaborate(self, platform):
m = Module()
m.d.comb += [
self.pfv.stb .eq(1),
self.pfv.insn.eq(Cat(Const(0, 32), self.insn.as_value())),
self.pfv.intr.eq(0),
self.pfv.nia .eq(iea(self.pfv.cia + 4, self.pfv.msr.r_data.sf)),
self.pfv.msr.r_mask.sf.eq(1),
]
if isinstance(self.insn, (
CRAND, CROR , CRNAND, CRXOR,
CRNOR, CRANDC, CREQV , CRORC,
)):
src_a = Signal()
src_b = Signal()
result = Signal()
m.d.comb += [
self.pfv.cr.r_mask[::-1].bit_select(self.insn.BA, width=1).eq(1),
self.pfv.cr.r_mask[::-1].bit_select(self.insn.BB, width=1).eq(1),
src_a.eq(self.pfv.cr.r_data[::-1].bit_select(self.insn.BA, width=1)),
src_b.eq(self.pfv.cr.r_data[::-1].bit_select(self.insn.BB, width=1)),
]
if isinstance(self.insn, CRAND):
m.d.comb += result.eq(src_a & src_b)
if isinstance(self.insn, CROR):
m.d.comb += result.eq(src_a | src_b)
if isinstance(self.insn, CRNAND):
m.d.comb += result.eq(~(src_a & src_b))
if isinstance(self.insn, CRXOR):
m.d.comb += result.eq(src_a ^ src_b)
if isinstance(self.insn, CRNOR):
m.d.comb += result.eq(~(src_a | src_b))
if isinstance(self.insn, CRANDC):
m.d.comb += result.eq(src_a & ~src_b)
if isinstance(self.insn, CREQV):
m.d.comb += result.eq(src_a == src_b)
if isinstance(self.insn, CRORC):
m.d.comb += result.eq(src_a | ~src_b)
m.d.comb += [
self.pfv.cr.w_mask[::-1].bit_select(self.insn.BT, width=1).eq(1),
self.pfv.cr.w_data[::-1].bit_select(self.insn.BT, width=1).eq(result),
]
elif isinstance(self.insn, MCRF):
field = Signal(4)
m.d.comb += [
field.eq(self.pfv.cr.r_data[::-1].word_select(self.insn.BFA, width=4)),
self.pfv.cr.r_mask[::-1].word_select(self.insn.BFA, width=4).eq(0b1111),
self.pfv.cr.w_mask[::-1].word_select(self.insn.BF, width=4).eq(0b1111),
self.pfv.cr.w_data[::-1].word_select(self.insn.BF, width=4).eq(field),
]
else:
assert False
return m