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97 lines
3.3 KiB
Python
97 lines
3.3 KiB
Python
2 years ago
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from amaranth import *
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from power_fv import pfv
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from power_fv.insn.const import *
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from power_fv.reg import xer_layout
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from . import InsnSpec
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from .utils import iea
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__all__ = ["SPRMoveSpec"]
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class SPRMoveSpec(InsnSpec, Elaboratable):
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def __init__(self, insn):
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self.pfv = pfv.Interface()
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self.insn = insn
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def elaborate(self, platform):
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m = Module()
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m.d.comb += [
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self.pfv.stb .eq(1),
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self.pfv.insn.eq(Cat(Const(0, 32), self.insn.as_value())),
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self.pfv.nia .eq(iea(self.pfv.cia + 4, self.pfv.msr.r_data.sf)),
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self.pfv.msr.r_mask.sf.eq(1),
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self.pfv.msr.r_mask.pr.eq(1),
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]
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# If SPR(0) = 1, this instruction is privileged.
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spr_privileged = Signal()
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spr_access_err = Signal()
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m.d.comb += [
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spr_privileged.eq(self.insn.SPR[9 - 0]),
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spr_access_err.eq(spr_privileged & self.pfv.msr.r_data.pr),
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self.pfv.intr.eq(spr_access_err),
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]
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def mXspr_spec(pfv_spr, mtspr_cls, mfspr_cls, reserved_mask):
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if isinstance(self.insn, mtspr_cls):
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# Copy (RS) to SPR.
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m.d.comb += [
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self.pfv.rs.index.eq(self.insn.RS),
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self.pfv.rs.r_stb.eq(1),
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pfv_spr.w_mask.eq(~reserved_mask),
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pfv_spr.w_data.eq(self.pfv.rs.r_data & ~reserved_mask),
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]
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if isinstance(self.insn, mfspr_cls):
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# Copy SPR to (RT).
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m.d.comb += [
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self.pfv.rt.index.eq(self.insn.RT),
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self.pfv.rt.w_stb.eq(1),
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pfv_spr.r_mask.eq(~reserved_mask),
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]
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# In problem state, reading reserved bits returns 0.
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with m.If(self.pfv.msr.r_data.pr):
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m.d.comb += self.pfv.rt.w_data.eq(pfv_spr.r_data & ~reserved_mask)
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with m.Else():
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m.d.comb += self.pfv.rt.w_data.eq(pfv_spr.r_data)
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if isinstance(self.insn, (MTXER, MFXER)):
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xer_reserved_mask = Record(xer_layout)
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m.d.comb += [
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xer_reserved_mask._56.eq(Repl(1, 1)),
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xer_reserved_mask._46.eq(Repl(1, 2)),
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xer_reserved_mask._35.eq(Repl(1, 9)),
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xer_reserved_mask._0 .eq(Repl(1, 32)),
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]
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mXspr_spec(self.pfv.xer, MTXER, MFXER, xer_reserved_mask)
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elif isinstance(self.insn, (MTLR, MFLR)):
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mXspr_spec(self.pfv.lr, MTLR, MFLR, Const(0, 64))
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elif isinstance(self.insn, (MTCTR, MFCTR)):
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mXspr_spec(self.pfv.ctr, MTCTR, MFCTR, Const(0, 64))
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elif isinstance(self.insn, (MTSRR0, MFSRR0)):
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mXspr_spec(self.pfv.srr0, MTSRR0, MFSRR0, Const(0, 64))
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elif isinstance(self.insn, (MTSRR1, MFSRR1)):
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# SRR1 bits should be treated as reserved if their corresponding MSR bits are also
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# reserved; which is implementation-specific.
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# We treat all bits as defined for now, but this may cause false positives.
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srr1_reserved_mask = Const(0, 64)
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mXspr_spec(self.pfv.srr1, MTSRR1, MFSRR1, srr1_reserved_mask)
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elif isinstance(self.insn, (MTTAR, MFTAR)):
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mXspr_spec(self.pfv.tar, MTTAR, MFTAR, Const(0, 64))
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else:
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assert False
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return m
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