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@ -5,47 +5,46 @@ from amaranth.asserts import *
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__all__ = ["Testbench"]
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def _check_triggers(t_start, t_pre, t_post):
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if not isinstance(t_start, int) or t_start <= 0:
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raise ValueError("t_start must be a positive integer, not {!r}"
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.format(t_start))
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if not isinstance(t_post, int) or t_post < t_start:
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raise ValueError("t_post must be an integer greater than or equal to t_start ({}), not {!r}"
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.format(t_start, t_post))
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if not isinstance(t_pre, int) or t_pre > t_post or t_pre < t_start:
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raise ValueError("t_pre must be an integer between t_start and t_post (i.e. [{},{}]), "
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"not {!r}".format(t_pre, t_start, t_post))
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class Testbench(Elaboratable):
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def __init__(self, check, dut, *, t_post, t_pre=None, t_start=0):
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if not isinstance(t_post, int) or t_post < 0:
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raise ValueError("t_post must be a non-negative integer, not {!r}"
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.format(t_post))
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if t_pre is None:
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def __init__(self, check, dut, *, t_start=1, t_pre=None, t_post=20):
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if t_pre is None and t_post is not None:
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t_pre = t_post
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if not isinstance(t_pre, int) or t_pre < 0:
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raise ValueError("t_pre must be a non-negative integer, not {!r}"
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.format(t_pre))
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if t_pre > t_post:
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raise ValueError("t_pre ({}) must be lesser than or equal to t_post ({})"
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.format(t_pre, t_post))
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if not isinstance(t_start, int) or t_start < 0:
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raise ValueError("t_start must be a non-negative integer, not {!r}"
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.format(t_start))
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if t_start > t_pre:
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raise ValueError("t_start ({}) must be lesser than or equal to t_pre ({})"
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.format(t_start, t_pre))
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self.t_post = t_post
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self.t_pre = t_pre
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self.t_start = t_start
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_check_triggers(t_start, t_pre, t_post)
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self.check = check
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self.dut = dut
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self.check = check
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self.dut = dut
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self.t_start = t_start
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self.t_pre = t_pre
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self.t_post = t_post
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def elaborate(self, platform):
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m = Module()
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timer = Signal(range(self.t_post + 1))
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with m.If(timer != self.t_post):
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timer = Signal(range(self.t_post + 2), reset=1)
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with m.If(timer <= self.t_post):
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m.d.sync += timer.eq(timer + 1)
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m.submodules.check = ResetInserter(timer < self.t_start)(self.check)
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m.submodules.dut = self.dut
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m.d.comb += [
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self.check.dut .eq(self.dut.pfv),
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self.check.pre .eq(timer == self.t_pre),
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self.check.post.eq(timer == self.t_post),
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self.check.pfv .eq(self.dut.pfv),
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]
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m.d.comb += Assume(ResetSignal() == Initial())
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