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148 lines
4.6 KiB
Python
148 lines
4.6 KiB
Python
import argparse
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import json
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import pathlib
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from amaranth import *
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from amaranth.sim import *
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from power_fv.test.model import Model
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__all__ = ["simulate"]
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def simulate(tests, *, vcd_file, mem_size=64):
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dut = Model(mem_size=mem_size, mem_aligned=True, muldiv_altops=True)
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sim = Simulator(dut)
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def read_reg(name):
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name = name.lower()
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assert name != "mem"
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if name.startswith("g"):
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return dut.ctx.gpr[int(name[1:])]
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elif hasattr(dut.ctx, name):
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reg = getattr(dut.ctx, name)
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return reg.as_value()
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else:
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return None # unimplemented
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def write_reg(name, value):
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name = name.lower()
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value = int(value, base=16)
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assert name != "mem"
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if name.startswith("g"):
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return dut.ctx.gpr[int(name[1:])].eq(value)
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elif hasattr(dut.ctx, name):
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reg = getattr(dut.ctx, name)
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return reg.eq(value)
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else:
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return Delay() # unimplemented
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def process():
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for test in tests:
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print("Running test {}...".format(test["name"]))
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# Initialize context
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if "inits" in test:
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for reg in test["inits"]["regs"]:
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yield write_reg(reg["name"], reg["val"])
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if test["inits"]["mem"]:
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raise NotImplementedError
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yield Delay()
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# Execute ops
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for op in test["ops"]:
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print(">", " ".join(op["text"]))
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# Check EA
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dut_ea = yield read_reg("IAR")
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tst_ea = int(op["ea"], base=16)
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if dut_ea != tst_ea:
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raise ValueError("EA mismatch: expected {}, got {}"
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.format(op["ea"], dut_ea))
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# Check reads
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for reg in op["regReads"]:
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dut_val = yield read_reg(reg["name"])
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tst_val = int(reg["val"], base=16)
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if dut_val is None:
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continue
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if dut_val != tst_val:
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raise ValueError("Read {} mismatch: expected {:#x}, got {:#x}"
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.format(reg["name"], tst_val, dut_val))
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if op["memReads"]:
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raise NotImplementedError
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# Execute instruction
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tst_opcode = Const(int(op["opcode"], base=16), 32)
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# FIXME(ASAP): OPV testcases use LE=1, but we only support BE; let's try anyway
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yield dut.insn.eq(Cat(tst_opcode.word_select(i, 8) for i in reversed(range(4))) << 32)
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# yield dut.insn.eq(tst_opcode << 32)
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yield dut.stb.eq(1)
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yield Delay()
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if (yield dut.err.insn):
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raise ValueError("Unknown/conflicting opcode: {:#x}"
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.format(tst_opcode))
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yield Tick()
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yield Delay()
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# Check writes
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for reg in op["regWrites"]:
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dut_val = yield read_reg(reg["name"])
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tst_val = int(reg["val"], base=16)
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if dut_val is None:
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continue
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if dut_val != tst_val:
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raise ValueError("Write {} mismatch: expected {:#x}, got {:#x}"
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.format(reg["name"], tst_val, dut_val))
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if op["memWrites"]:
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raise NotImplementedError
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# Check results
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if "results" in test:
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for reg in test["results"]["regs"]:
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dut_val = yield read_reg(reg["name"])
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tst_val = int(reg["val"], base=16)
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if dut_val is None:
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continue
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if dut_val != tst_val:
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raise ValueError("Result {} mismatch: expected {:#x}, got {:#x}"
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.format(reg["name"], tst_val, dut_val))
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if test["results"]["mem"]:
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raise NotImplementedError
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yield dut.stb.eq(0)
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yield Delay()
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sim.add_clock(1e-6)
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sim.add_sync_process(process)
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with sim.write_vcd(vcd_file):
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sim.run()
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if __name__ == "__main__":
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parser = argparse.ArgumentParser()
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parser.add_argument("input", type=pathlib.Path)
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parser.add_argument("-o", "--output", type=argparse.FileType("w"))
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args = parser.parse_args()
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with open(args.input, "r") as f:
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tests = json.loads(f.read())
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simulate(tests, vcd_file=args.output)
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