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211 lines
6.8 KiB
Python
211 lines
6.8 KiB
Python
from amaranth import *
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from amaranth.asserts import *
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from .. import pfv
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from ..insn import *
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__all__ = ["Check"]
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class Check(Elaboratable):
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_insn_cls = None
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def __init_subclass__(cls, *, insn_cls):
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cls._insn_cls = insn_cls
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def __init__(self):
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self.pfv = pfv.Interface()
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self.trig = Record([
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("pre", 1),
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("post", 1),
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])
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def elaborate(self, platform):
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m = Module()
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# TODO:
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# - support MSR (stop assuming 64-bit mode)
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# - support interrupts (detect illegal forms)
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spec_insn = self._insn_cls()
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with m.If(self.trig.post):
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m.d.sync += [
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Assume(self.pfv.stb),
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Assume(self.pfv.insn[32:] == spec_insn),
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]
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if isinstance(spec_insn, (Instruction_B, Instruction_XL_b)):
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bo_valid_patterns = [
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"0000-",
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"0001-",
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"001--",
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"0100-",
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"0101-",
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"011--",
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"1-00-",
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"1-01-"
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]
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if not isinstance(spec_insn, Instruction_B):
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# "Branch always" mnemonics are undefined for B-form conditional branches.
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# (Appendix C.2.2, Book I)
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bo_valid_patterns.append("1-1--")
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bo_valid = Signal()
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m.d.comb += bo_valid.eq(spec_insn.bo.matches(*bo_valid_patterns))
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# FIXME(microwatt,interrupts): turn this into an assert
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with m.If(self.trig.post):
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m.d.sync += Assume(bo_valid | self.pfv.intr)
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# NIA
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spec_nia = Signal(unsigned(64))
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taken = Signal()
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offset = Signal(signed(62))
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if isinstance(spec_insn, Instruction_I):
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m.d.comb += [
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taken .eq(1),
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offset.eq(spec_insn.li)
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]
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elif isinstance(spec_insn, (Instruction_B, Instruction_XL_b)):
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cond_bit = Signal()
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ctr_any = Signal()
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cond_ok = Signal()
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ctr_ok = Signal()
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m.d.comb += [
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cond_bit.eq(self.pfv.cr.r_data[::-1].bit_select(spec_insn.bi, width=1)),
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ctr_any .eq(self.pfv.ctr.w_data.any()),
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cond_ok .eq(spec_insn.bo[4] | (spec_insn.bo[3] == cond_bit)),
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ctr_ok .eq(spec_insn.bo[2] | (ctr_any ^ spec_insn.bo[1])),
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]
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if isinstance(spec_insn, Instruction_XL_b) and spec_insn.xo.value == 528: # bcctr/bcctrl
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m.d.comb += taken.eq(cond_ok)
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else:
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m.d.comb += taken.eq(cond_ok & ctr_ok)
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if isinstance(spec_insn, Instruction_B):
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m.d.comb += offset.eq(spec_insn.bd)
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elif spec_insn.xo.value == 16: # bclr/bclrl
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m.d.comb += offset.eq(self.pfv.lr .r_data[:61])
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elif spec_insn.xo.value == 528: # bcctr/bcctrl
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m.d.comb += offset.eq(self.pfv.ctr.r_data[:61])
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elif spec_insn.xo.value == 560: # bctar/bctarl
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m.d.comb += offset.eq(self.pfv.tar.r_data[:61])
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else:
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assert False
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else:
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assert False
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with m.If(taken):
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if isinstance(spec_insn, (Instruction_I, Instruction_B)) and spec_insn.aa.value == 0:
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m.d.comb += spec_nia.eq(self.pfv.cia + (offset << 2))
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else:
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m.d.comb += spec_nia.eq(offset << 2)
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with m.Else():
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m.d.comb += spec_nia.eq(self.pfv.cia + 4)
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with m.If(self.trig.post & ~self.pfv.intr):
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m.d.sync += Assert(self.pfv.nia == spec_nia)
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# CR
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spec_cr_r_stb = Signal(8)
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if isinstance(spec_insn, Instruction_I):
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m.d.comb += spec_cr_r_stb.eq(0)
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elif isinstance(spec_insn, (Instruction_B, Instruction_XL_b)):
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m.d.comb += spec_cr_r_stb[::-1].bit_select(spec_insn.bi[2:], width=1).eq(1)
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else:
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assert False
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with m.If(self.trig.post & ~self.pfv.intr):
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for i, spec_cr_r_stb_bit in enumerate(spec_cr_r_stb):
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pfv_cr_r_stb_bit = self.pfv.cr.r_stb[i]
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m.d.sync += Assert(spec_cr_r_stb_bit.implies(pfv_cr_r_stb_bit))
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# LR
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spec_lr_r_stb = Signal()
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spec_lr_w_stb = Signal()
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spec_lr_w_data = Signal(64)
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if isinstance(spec_insn, (Instruction_I, Instruction_B)):
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m.d.comb += spec_lr_r_stb.eq(0)
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elif isinstance(spec_insn, (Instruction_XL_b)):
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m.d.comb += spec_lr_r_stb.eq(spec_insn.xo == 16) # bclr/bclrl
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else:
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assert False
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m.d.comb += [
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spec_lr_w_stb .eq(spec_insn.lk),
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spec_lr_w_data.eq(self.pfv.cia + 4),
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]
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with m.If(self.trig.post & ~self.pfv.intr):
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m.d.sync += [
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Assert(self.pfv.lr.r_stb == spec_lr_r_stb),
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Assert(self.pfv.lr.w_stb == spec_lr_w_stb),
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Assert(self.pfv.lr.w_stb.implies(self.pfv.lr.w_data == spec_lr_w_data)),
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]
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# CTR
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spec_ctr_r_stb = Signal()
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spec_ctr_w_stb = Signal()
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spec_ctr_w_data = Signal(64)
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if isinstance(spec_insn, Instruction_I):
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m.d.comb += spec_ctr_r_stb.eq(0)
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elif isinstance(spec_insn, Instruction_B):
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m.d.comb += spec_ctr_r_stb.eq(~spec_insn.bo[2])
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elif isinstance(spec_insn, (Instruction_B, Instruction_XL_b)):
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m.d.comb += spec_ctr_r_stb.eq(1)
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else:
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assert False
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if isinstance(spec_insn, Instruction_I):
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m.d.comb += spec_ctr_w_stb.eq(0)
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elif isinstance(spec_insn, Instruction_B):
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m.d.comb += spec_ctr_w_stb.eq(~spec_insn.bo[2])
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elif isinstance(spec_insn, Instruction_XL_b):
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if spec_insn.xo.value == 528: # bcctr/bcctrl
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m.d.comb += spec_ctr_w_stb.eq(0)
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else:
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m.d.comb += spec_ctr_w_stb.eq(~spec_insn.bo[2])
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else:
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assert False
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m.d.comb += spec_ctr_w_data.eq(self.pfv.ctr.r_data - 1)
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with m.If(self.trig.post & ~self.pfv.intr):
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m.d.sync += [
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Assert(self.pfv.ctr.r_stb == spec_ctr_r_stb),
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Assert(self.pfv.ctr.w_stb == spec_ctr_w_stb),
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Assert(self.pfv.ctr.w_stb.implies(self.pfv.ctr.w_data == spec_ctr_w_data)),
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]
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# TAR
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spec_tar_r_stb = Signal()
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if isinstance(spec_insn, (Instruction_I, Instruction_B)):
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m.d.comb += spec_tar_r_stb.eq(0)
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elif isinstance(spec_insn, (Instruction_XL_b)):
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m.d.comb += spec_tar_r_stb.eq(spec_insn.xo == 560) # bctar/bctarl
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else:
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assert False
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with m.If(self.trig.post & ~self.pfv.intr):
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m.d.sync += [
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Assert(self.pfv.tar.r_stb == spec_tar_r_stb),
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]
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return m
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