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toy-sram
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add gen parm for 16x12 or 32x12 subarray

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master
openpowerwtf 2 years ago
parent 685d4a98c4
commit 2e11a03ffb
8 changed files with 521 additions and 412 deletions
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60
rtl/sim/coco/ra_shard_64x72_2r1w.gtkw
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@ -1,24 +1,27 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Tue Nov 15 19:51:18 2022
[*] Wed Nov 16 17:14:03 2022
[*]
[dumpfile] "/data/projects/toy-sram/rtl/sim/coco/tb_ra_64x72.fst"
[dumpfile_mtime] "Tue Nov 15 19:33:55 2022"
[dumpfile_size] 99807
[dumpfile_mtime] "Wed Nov 16 16:47:59 2022"
[dumpfile_size] 13040
[savefile] "/data/projects/toy-sram/rtl/sim/coco/ra_shard_64x72_2r1w.gtkw"
[timestart] 0
[timestart] 86274
[size] 1699 1047
[pos] 188 267
*-12.000000 1020 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-10.000000 90500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ra_64x72_2r1w.
[treeopen] tb_ra_64x72_2r1w.lcb.
[treeopen] tb_ra_64x72_2r1w.ra.
[treeopen] tb_ra_64x72_2r1w.ra.ra0.
[treeopen] tb_ra_64x72_2r1w.ra.ra0.r000.
[treeopen] tb_ra_64x72_2r1w.ra.ra0.genblk1.
[treeopen] tb_ra_64x72_2r1w.ra.ra1.
[treeopen] tb_ra_64x72_2r1w.ra.ra2.
[treeopen] tb_ra_64x72_2r1w.ra.ra2.genblk1.
[sst_width] 242
[signals_width] 257
[signals_width] 387
[sst_expanded] 1
[sst_vpaned_height] 301
[sst_vpaned_height] 331
@28
tb_ra_64x72_2r1w.clk
tb_ra_64x72_2r1w.rd_enb_0
@ -44,12 +47,7 @@ tb_ra_64x72_2r1w.cnfig.cfg[0:31]
-LCB
@22
tb_ra_64x72_2r1w.lcb.tap1_sel_q[0:3]
@23
tb_ra_64x72_2r1w.lcb.tap1[0:3]
@28
tb_ra_64x72_2r1w.lcb.tap1_b
tb_ra_64x72_2r1w.lcb.pulse1_b
tb_ra_64x72_2r1w.lcb.pulse2_b
tb_ra_64x72_2r1w.lcb.strobe
@200
-RA
@ -57,6 +55,21 @@ tb_ra_64x72_2r1w.lcb.strobe
tb_ra_64x72_2r1w.ra.rd_enb_0_q
@22
tb_ra_64x72_2r1w.ra.rd_adr_0_q[0:5]
@28
tb_ra_64x72_2r1w.rd_enb_0
@23
tb_ra_64x72_2r1w.ra.ra2.genblk1.r00.mem_30[0:11]
@22
tb_ra_64x72_2r1w.ra.ra2.genblk1.r01.mem_30[0:11]
tb_ra_64x72_2r1w.ra.ra2.genblk1.r00.RBL0[0:11]
tb_ra_64x72_2r1w.ra.ra2.genblk1.r01.RBL0[0:11]
tb_ra_64x72_2r1w.ra.ra2.rbl0_00_31_12_23[0:11]
tb_ra_64x72_2r1w.ra.ra2.rbl0_32_63_00_11[0:11]
tb_ra_64x72_2r1w.ra.ra2.rbl0_32_63_12_23[0:11]
tb_ra_64x72_2r1w.ra.ra0.rd0_dat[0:23]
tb_ra_64x72_2r1w.ra.ra1.rd0_dat[0:23]
tb_ra_64x72_2r1w.ra.ra2.rd0_dat[0:23]
tb_ra_64x72_2r1w.rd_dat_0[0:71]
tb_ra_64x72_2r1w.ra.rd_dat_0_q[0:71]
@28
tb_ra_64x72_2r1w.ra.rd_enb_1_q
@ -72,26 +85,13 @@ tb_ra_64x72_2r1w.ra.wr_dat_0_q[0:71]
-RA0
@28
tb_ra_64x72_2r1w.ra.ra0.rd1_c_a0
tb_ra_64x72_2r1w.ra.ra0.rd1_c_a0_i
tb_ra_64x72_2r1w.ra.ra0.rd1_c_na0_i
@22
tb_ra_64x72_2r1w.ra.ra0.rbl1_000[0:11]
@200
-R000
@22
tb_ra_64x72_2r1w.ra.ra0.r000.mem_00[0:11]
tb_ra_64x72_2r1w.ra.ra0.r000.RWL0[0:15]
tb_ra_64x72_2r1w.ra.ra0.r000.RWL1[0:15]
tb_ra_64x72_2r1w.ra.ra0.r000.RBL0[0:11]
tb_ra_64x72_2r1w.ra.ra0.r000.RBL1[0:11]
tb_ra_64x72_2r1w.ra.ra0.r000.WWL[0:15]
tb_ra_64x72_2r1w.ra.ra0.r000.WBL[0:11]
tb_ra_64x72_2r1w.ra.ra0.r000.WBLb[0:11]
@200
-Eval
@22
tb_ra_64x72_2r1w.ra.ra0.eval_0x0.RBL1_L[0:11]
tb_ra_64x72_2r1w.ra.ra0.eval_0x0.RBL1_R[0:11]
tb_ra_64x72_2r1w.ra.ra0.eval_0x0.RBL1_O_b[0:11]
tb_ra_64x72_2r1w.ra.ra0.genblk1.r00.mem_00[0:11]
tb_ra_64x72_2r1w.ra.ra0.genblk1.r01.mem_00[0:11]
tb_ra_64x72_2r1w.ra.ra0.genblk1.r10.mem_00[0:11]
tb_ra_64x72_2r1w.ra.ra0.genblk1.r11.mem_00[0:11]
[pattern_trace] 1
[pattern_trace] 0

6
rtl/sim/coco/results.xml
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@ -1,8 +1,6 @@
<testsuites name="results">
<testsuite name="all" package="all">
<property name="random_seed" value="1668540834" />
<testcase name="tb" classname="tb_ra_64x72" file="/data/projects/toy-sram/rtl/sim/coco/tb_ra_64x72.py" lineno="293" time="0.2973616123199463" sim_time_ns="107.001" ratio_time="359.8346106789072">
<failure />
</testcase>
<property name="random_seed" value="1668630103" />
<testcase name="tb" classname="tb_ra_64x72" file="/data/projects/toy-sram/rtl/sim/coco/tb_ra_64x72.py" lineno="293" time="22.16532826423645" sim_time_ns="10089.001" ratio_time="455.1703850142616" />
</testsuite>
</testsuites>

BIN
rtl/sim/coco/tb_ra_64x72.fst
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Binary file not shown.

2
rtl/sim/coco/tb_ra_64x72.py
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@ -377,8 +377,10 @@ async def tb(dut):
# configure allowed ports/entries
rangesRd = [(0,63), (0,63), (0,63), (0,63)] # full
#rangesRd = [(0,7), (0,7), (0,7), (0,7)] # hammer
#rangesRd = [(0,0), (0,0), (0,0), (0,0)] # single
rangesWr = [(0,63), (0,63),(0,63), (0,63)] # full
#rangesWr = [(0,7), (0,7)] # hammer
#rangesWr = [(0,0), (0,0)] # single
#rangesWr = [None, None] # none

verbose = True

150
rtl/src/array/regfile_64x24_2r1w.v
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@ -22,9 +22,9 @@

`timescale 1 ps / 1 ps

// 0: gen 8x 16x12 plus local eval 1: gen 4x 32x24 and no local eval
// 0: gen 8x 16x12 plus local eval 1: gen 4x 32x12 and no local eval
module regfile_64x24_2r1w #(
parameter integer RA_32x24 = 1
parameter integer RA_32x12 = 1
) (

input rd0_c_na0,
@ -71,8 +71,9 @@ module regfile_64x24_2r1w #(

);

// word & bit selects
// word & bit selects

// 16x12
wire [0:15] rwl0_00_15_00_11;
wire [0:15] rwl0_00_15_12_23;
wire [0:15] rwl1_00_15_00_11;
@ -125,7 +126,21 @@ wire [0:11] rbl1_48_63_12_23;
wire [0:11] wbl_48_63_00_11;
wire [0:11] wbl_48_63_12_23;

// 32x24
// 32x12
wire [0:31] rwl0_00_31_00_11;
wire [0:31] rwl0_00_31_12_23;
wire [0:31] rwl1_00_31_00_11;
wire [0:31] rwl1_00_31_12_23;
wire [0:31] wwl_00_31_00_11;
wire [0:31] wwl_00_31_12_23;

wire [0:31] rwl0_32_63_00_11;
wire [0:31] rwl0_32_63_12_23;
wire [0:31] rwl1_32_63_00_11;
wire [0:31] rwl1_32_63_12_23;
wire [0:31] wwl_32_63_00_11;
wire [0:31] wwl_32_63_12_23;

wire [0:11] rbl0_00_31_00_11;
wire [0:11] rbl0_00_31_12_23;
wire [0:11] rbl1_00_31_00_11;
@ -140,13 +155,17 @@ wire [0:11] rbl1_32_63_12_23;
wire [0:11] wbl_32_63_00_11;
wire [0:11] wbl_32_63_12_23;

genvar i;

// subarrays
generate

if (RA_32x24 == 0) begin
// subarray cells; 4x2 16w/12b subarrays
if (RA_32x12 == 0) begin

// 4x2 16w/12b

// words 00:15
toysram_16x12 r000 (
// words 00:15
toysram_16x12 r000 (
.RWL0(rwl0_00_15_00_11),
.RWL1(rwl1_00_15_00_11),
.WWL(wwl_00_15_00_11),
@ -154,8 +173,8 @@ toysram_16x12 r000 (
.RBL1(rbl1_00_15_00_11),
.WBL(wbl_00_15_00_11),
.WBLb(~wbl_00_15_00_11)
);
toysram_16x12 r001 (
);
toysram_16x12 r001 (
.RWL0(rwl0_00_15_12_23),
.RWL1(rwl1_00_15_12_23),
.WWL(wwl_00_15_12_23),
@ -163,10 +182,10 @@ toysram_16x12 r001 (
.RBL1(rbl1_00_15_12_23),
.WBL(wbl_00_15_12_23),
.WBLb(~wbl_00_15_12_23)
);
);

// words 16:31
toysram_16x12 r010 (
// words 16:31
toysram_16x12 r010 (
.RWL0(rwl0_16_31_00_11),
.RWL1(rwl1_16_31_00_11),
.WWL(wwl_16_31_00_11),
@ -174,8 +193,8 @@ toysram_16x12 r010 (
.RBL1(rbl1_16_31_00_11),
.WBL(wbl_16_31_00_11),
.WBLb(~wbl_16_31_00_11)
);
toysram_16x12 r011 (
);
toysram_16x12 r011 (
.RWL0(rwl0_16_31_12_23),
.RWL1(rwl1_16_31_12_23),
.WWL(wwl_16_31_12_23),
@ -183,10 +202,10 @@ toysram_16x12 r011 (
.RBL1(rbl1_16_31_12_23),
.WBL(wbl_16_31_12_23),
.WBLb(~wbl_16_31_12_23)
);
);

// words 32:47
toysram_16x12 r100 (
// words 32:47
toysram_16x12 r100 (
.RWL0(rwl0_32_47_00_11),
.RWL1(rwl1_32_47_00_11),
.WWL(wwl_32_47_00_11),
@ -194,8 +213,8 @@ toysram_16x12 r100 (
.RBL1(rbl1_32_47_00_11),
.WBL(wbl_32_47_00_11),
.WBLb(~wbl_32_47_00_11)
);
toysram_16x12 r101 (
);
toysram_16x12 r101 (
.RWL0(rwl0_32_47_12_23),
.RWL1(rwl1_32_47_12_23),
.WWL(wwl_32_47_12_23),
@ -203,10 +222,10 @@ toysram_16x12 r101 (
.RBL1(rbl1_32_47_12_23),
.WBL(wbl_32_47_12_23),
.WBLb(~wbl_32_47_12_23)
);
);

// words 48:63
toysram_16x12 r110 (
// words 48:63
toysram_16x12 r110 (
.RWL0(rwl0_48_63_00_11),
.RWL1(rwl1_48_63_00_11),
.WWL(wwl_48_63_00_11),
@ -214,8 +233,8 @@ toysram_16x12 r110 (
.RBL1(rbl1_48_63_00_11),
.WBL(wbl_48_63_00_11),
.WBLb(~wbl_48_63_00_11)
);
toysram_16x12 r111 (
);
toysram_16x12 r111 (
.RWL0(rwl0_48_63_12_23),
.RWL1(rwl1_48_63_12_23),
.WWL(wwl_48_63_12_23),
@ -223,14 +242,14 @@ toysram_16x12 r111 (
.RBL1(rbl1_48_63_12_23),
.WBL(wbl_48_63_12_23),
.WBLb(~wbl_48_63_12_23)
);
);

end else begin

// subarray cells; 2x2 32w/24b subarrays w/local eval inside between pairs
// 2x2 32w/24b w/local eval inside between pairs

// words 00:31
toysram_32x12 r00 (
// words 00:31
toysram_32x12 r00 (
.RWL0({rwl0_00_15_00_11,rwl0_16_31_00_11}),
.RWL1({rwl1_00_15_00_11,rwl1_16_31_00_11}),
.WWL({wwl_00_15_00_11,wwl_16_31_00_11}),
@ -238,9 +257,9 @@ toysram_32x12 r00 (
.RBL1(rbl1_00_31_00_11),
.WBL(wbl_00_31_00_11),
.WBLb(~wbl_00_31_00_11)
);
);

toysram_32x12 r01 (
toysram_32x12 r01 (
.RWL0({rwl0_00_15_12_23,rwl0_16_31_12_23}),
.RWL1({rwl1_00_15_12_23,rwl1_16_31_12_23}),
.WWL({wwl_00_15_12_23,wwl_16_31_12_23}),
@ -248,21 +267,21 @@ toysram_32x12 r01 (
.RBL1(rbl1_00_31_12_23),
.WBL(wbl_00_31_12_23),
.WBLb(~wbl_00_31_12_23)
);
);

// words 32:47
toysram_32x12 r10 (
.RWL0({rwl0_32_47_00_11,rwl0_48_31_00_11}),
.RWL1({rwl1_32_47_00_11,rwl1_48_31_00_11}),
.WWL({wwl_32_47_00_11,wwl_48_31_00_11}),
// words 32:47
toysram_32x12 r10 (
.RWL0({rwl0_32_47_00_11,rwl0_48_63_00_11}),
.RWL1({rwl1_32_47_00_11,rwl1_48_63_00_11}),
.WWL({wwl_32_47_00_11,wwl_48_63_00_11}),
.RBL0(rbl0_32_63_00_11),
.RBL1(rbl1_32_63_00_11),
.WBL(wbl_32_63_00_11),
.WBLb(~wbl_32_63_00_11)
);
);

// words 48:63
toysram_32x12 r11 (
// words 48:63
toysram_32x12 r11 (
.RWL0({rwl0_32_47_12_23,rwl0_48_63_12_23}),
.RWL1({rwl1_32_47_12_23,rwl1_48_63_12_23}),
.WWL({wwl_32_47_12_23,wwl_48_63_12_23}),
@ -270,7 +289,7 @@ toysram_32x12 r11 (
.RBL1(rbl1_32_63_12_23),
.WBL(wbl_32_63_12_23),
.WBLb(~wbl_32_63_12_23)
);
);

end
endgenerate
@ -549,31 +568,48 @@ assign rwl0_48_63_12_23 = rwl0_48_63_00_11;
assign rwl1_48_63_12_23 = rwl1_48_63_00_11;
assign wwl_48_63_12_23 = wwl_48_63_00_11;


// bit lines

genvar i;
generate

for (i = 0; i < 12; i = i + 1) begin
if (RA_32x12 == 0) begin

for (i = 0; i < 12; i = i + 1) begin
assign rd0_dat[i] = (~rbl0_00_15_00_11[i]) | (~rbl0_16_31_00_11[i]) | (~rbl0_32_47_00_11[i]) | (~rbl0_48_63_00_11[i]);
assign rd1_dat[i] = (~rbl1_00_15_00_11[i]) | (~rbl1_16_31_00_11[i]) | (~rbl1_32_47_00_11[i]) | (~rbl1_48_63_00_11[i]);
end
end

for (i = 0; i < 12; i = i + 1) begin
for (i = 0; i < 12; i = i + 1) begin
assign rd0_dat[i+12] = (~rbl0_00_15_12_23[i]) | (~rbl0_16_31_12_23[i]) | (~rbl0_32_47_12_23[i]) | (~rbl0_48_63_12_23[i]);
assign rd1_dat[i+12] = (~rbl1_00_15_12_23[i]) | (~rbl1_16_31_12_23[i]) | (~rbl1_32_47_12_23[i]) | (~rbl1_48_63_12_23[i]);
end
end

endgenerate
assign wbl_00_15_00_11 = wr0_dat[0:11];
assign wbl_00_15_12_23 = wr0_dat[12:23];
assign wbl_16_31_00_11 = wr0_dat[0:11];
assign wbl_16_31_12_23 = wr0_dat[12:23];
assign wbl_32_47_00_11 = wr0_dat[0:11];
assign wbl_32_47_12_23 = wr0_dat[12:23];
assign wbl_48_63_00_11 = wr0_dat[0:11];
assign wbl_48_63_12_23 = wr0_dat[12:23];

assign wbl_00_15_00_11 = wr0_dat[0:11];
assign wbl_00_15_12_23 = wr0_dat[12:23];
assign wbl_16_31_00_11 = wr0_dat[0:11];
assign wbl_16_31_12_23 = wr0_dat[12:23];
assign wbl_32_47_00_11 = wr0_dat[0:11];
assign wbl_32_47_12_23 = wr0_dat[12:23];
assign wbl_48_63_00_11 = wr0_dat[0:11];
assign wbl_48_63_12_23 = wr0_dat[12:23];
end else begin

for (i = 0; i < 12; i = i + 1) begin
assign rd0_dat[i] = rbl0_00_31_00_11[i] | rbl0_32_63_00_11[i];
assign rd1_dat[i] = rbl1_00_31_00_11[i] | rbl1_32_63_00_11[i];
end

for (i = 0; i < 12; i = i + 1) begin
assign rd0_dat[i+12] = rbl0_00_31_12_23[i] | rbl0_32_63_12_23[i];
assign rd1_dat[i+12] = rbl1_00_31_12_23[i] | rbl1_32_63_12_23[i];
end

assign wbl_00_31_00_11 = wr0_dat[0:11];
assign wbl_00_31_12_23 = wr0_dat[12:23];
assign wbl_32_63_00_11 = wr0_dat[0:11];
assign wbl_32_63_12_23 = wr0_dat[12:23];

end
endgenerate

endmodule

32
rtl/src/array/toysram_16x12.v
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@ -88,67 +88,67 @@ assign RBL1 = ~(mem_00 & {12{RWL1[0]}}) &
~(mem_15 & {12{RWL1[15]}});

always @(posedge WWL[0]) begin
mem_00 <= ~WBLb;
mem_00 <= WBL | ~WBLb;
end

always @(posedge WWL[1]) begin
mem_01 <= ~WBLb;
mem_01 <= WBL | ~WBLb;
end

always @(posedge WWL[2]) begin
mem_02 <= ~WBLb;
mem_02 <= WBL | ~WBLb;
end

always @(posedge WWL[3]) begin
mem_03 <= ~WBLb;
mem_03 <= WBL | ~WBLb;
end

always @(posedge WWL[4]) begin
mem_04 <= ~WBLb;
mem_04 <= WBL | ~WBLb;
end

always @(posedge WWL[5]) begin
mem_05 <= ~WBLb;
mem_05 <= WBL | ~WBLb;
end

always @(posedge WWL[6]) begin
mem_06 <= ~WBLb;
mem_06 <= WBL | ~WBLb;
end

always @(posedge WWL[7]) begin
mem_07 <= ~WBLb;
mem_07 <= WBL | ~WBLb;
end

always @(posedge WWL[8]) begin
mem_08 <= ~WBLb;
mem_08 <= WBL | ~WBLb;
end

always @(posedge WWL[9]) begin
mem_09 <= ~WBLb;
mem_09 <= WBL | ~WBLb;
end

always @(posedge WWL[10]) begin
mem_10 <= ~WBLb;
mem_10 <= WBL | ~WBLb;
end

always @(posedge WWL[11]) begin
mem_11 <= ~WBLb;
mem_11 <= WBL | ~WBLb;
end

always @(posedge WWL[12]) begin
mem_12 <= ~WBLb;
mem_12 <= WBL | ~WBLb;
end

always @(posedge WWL[13]) begin
mem_13 <= ~WBLb;
mem_13 <= WBL | ~WBLb;
end

always @(posedge WWL[14]) begin
mem_14 <= ~WBLb;
mem_14 <= WBL | ~WBLb;
end

always @(posedge WWL[15]) begin
mem_15 <= ~WBLb;
mem_15 <= WBL | ~WBLb;
end

// assert errors (multiwrite, etc.)

133
rtl/src/array/toysram_32x12.v
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@ -67,168 +67,167 @@ reg [0:11] mem_30;
reg [0:11] mem_31;

// word-select
// the bits are negative-active at this point in the 16x12 but
// the local eval is done between subarray pairs, so bits are positive going out
assign RBL0 = ~((mem_00 & {12{RWL0[0]}}) & (mem_16 & {12{RWL0[16]}})) &
~((mem_01 & {12{RWL0[1]}}) & (mem_17 & {12{RWL0[17]}})) &
~((mem_02 & {12{RWL0[2]}}) & (mem_18 & {12{RWL0[18]}})) &
~((mem_03 & {12{RWL0[3]}}) & (mem_19 & {12{RWL0[19]}})) &
~((mem_04 & {12{RWL0[4]}}) & (mem_20 & {12{RWL0[20]}})) &
~((mem_05 & {12{RWL0[5]}}) & (mem_21 & {12{RWL0[21]}})) &
~((mem_06 & {12{RWL0[6]}}) & (mem_22 & {12{RWL0[22]}})) &
~((mem_07 & {12{RWL0[7]}}) & (mem_23 & {12{RWL0[23]}})) &
~((mem_08 & {12{RWL0[8]}}) & (mem_24 & {12{RWL0[24]}})) &
~((mem_09 & {12{RWL0[9]}}) & (mem_25 & {12{RWL0[25]}})) &
~((mem_10 & {12{RWL0[10]}}) & (mem_26 & {12{RWL0[26]}})) &
~((mem_11 & {12{RWL0[11]}}) & (mem_27 & {12{RWL0[27]}})) &
~((mem_12 & {12{RWL0[12]}}) & (mem_28 & {12{RWL0[28]}})) &
~((mem_13 & {12{RWL0[13]}}) & (mem_29 & {12{RWL0[29]}})) &
~((mem_14 & {12{RWL0[14]}}) & (mem_30 & {12{RWL0[30]}})) &
~((mem_15 & {12{RWL0[15]}}) & (mem_31 & {12{RWL0[31]}}));

assign RBL0 = ~((mem_00 & {12{RWL1[0]}}) & (mem_16 & {12{RWL1[16]}})) &
~((mem_01 & {12{RWL1[1]}}) & (mem_17 & {12{RWL1[17]}})) &
~((mem_02 & {12{RWL1[2]}}) & (mem_18 & {12{RWL1[18]}})) &
~((mem_03 & {12{RWL1[3]}}) & (mem_19 & {12{RWL1[19]}})) &
~((mem_04 & {12{RWL1[4]}}) & (mem_20 & {12{RWL1[20]}})) &
~((mem_05 & {12{RWL1[5]}}) & (mem_21 & {12{RWL1[21]}})) &
~((mem_06 & {12{RWL1[6]}}) & (mem_22 & {12{RWL1[22]}})) &
~((mem_07 & {12{RWL1[7]}}) & (mem_23 & {12{RWL1[23]}})) &
~((mem_08 & {12{RWL1[8]}}) & (mem_24 & {12{RWL1[24]}})) &
~((mem_09 & {12{RWL1[9]}}) & (mem_25 & {12{RWL1[25]}})) &
~((mem_10 & {12{RWL1[10]}}) & (mem_26 & {12{RWL1[26]}})) &
~((mem_11 & {12{RWL1[11]}}) & (mem_27 & {12{RWL1[27]}})) &
~((mem_12 & {12{RWL1[12]}}) & (mem_28 & {12{RWL1[28]}})) &
~((mem_13 & {12{RWL1[13]}}) & (mem_29 & {12{RWL1[29]}})) &
~((mem_14 & {12{RWL1[14]}}) & (mem_30 & {12{RWL1[30]}})) &
~((mem_15 & {12{RWL1[15]}}) & (mem_31 & {12{RWL1[31]}}));
// the local eval is done between subarray pairs, and bits are positive going out
assign RBL0 = ((mem_00 & {12{RWL0[0]}}) | (mem_16 & {12{RWL0[16]}})) |
((mem_01 & {12{RWL0[1]}}) | (mem_17 & {12{RWL0[17]}})) |
((mem_02 & {12{RWL0[2]}}) | (mem_18 & {12{RWL0[18]}})) |
((mem_03 & {12{RWL0[3]}}) | (mem_19 & {12{RWL0[19]}})) |
((mem_04 & {12{RWL0[4]}}) | (mem_20 & {12{RWL0[20]}})) |
((mem_05 & {12{RWL0[5]}}) | (mem_21 & {12{RWL0[21]}})) |
((mem_06 & {12{RWL0[6]}}) | (mem_22 & {12{RWL0[22]}})) |
((mem_07 & {12{RWL0[7]}}) | (mem_23 & {12{RWL0[23]}})) |
((mem_08 & {12{RWL0[8]}}) | (mem_24 & {12{RWL0[24]}})) |
((mem_09 & {12{RWL0[9]}}) | (mem_25 & {12{RWL0[25]}})) |
((mem_10 & {12{RWL0[10]}}) | (mem_26 & {12{RWL0[26]}})) |
((mem_11 & {12{RWL0[11]}}) | (mem_27 & {12{RWL0[27]}})) |
((mem_12 & {12{RWL0[12]}}) | (mem_28 & {12{RWL0[28]}})) |
((mem_13 & {12{RWL0[13]}}) | (mem_29 & {12{RWL0[29]}})) |
((mem_14 & {12{RWL0[14]}}) | (mem_30 & {12{RWL0[30]}})) |
((mem_15 & {12{RWL0[15]}}) | (mem_31 & {12{RWL0[31]}}));

assign RBL1 = ((mem_00 & {12{RWL1[0]}}) | (mem_16 & {12{RWL1[16]}})) |
((mem_01 & {12{RWL1[1]}}) | (mem_17 & {12{RWL1[17]}})) |
((mem_02 & {12{RWL1[2]}}) | (mem_18 & {12{RWL1[18]}})) |
((mem_03 & {12{RWL1[3]}}) | (mem_19 & {12{RWL1[19]}})) |
((mem_04 & {12{RWL1[4]}}) | (mem_20 & {12{RWL1[20]}})) |
((mem_05 & {12{RWL1[5]}}) | (mem_21 & {12{RWL1[21]}})) |
((mem_06 & {12{RWL1[6]}}) | (mem_22 & {12{RWL1[22]}})) |
((mem_07 & {12{RWL1[7]}}) | (mem_23 & {12{RWL1[23]}})) |
((mem_08 & {12{RWL1[8]}}) | (mem_24 & {12{RWL1[24]}})) |
((mem_09 & {12{RWL1[9]}}) | (mem_25 & {12{RWL1[25]}})) |
((mem_10 & {12{RWL1[10]}}) | (mem_26 & {12{RWL1[26]}})) |
((mem_11 & {12{RWL1[11]}}) | (mem_27 & {12{RWL1[27]}})) |
((mem_12 & {12{RWL1[12]}}) | (mem_28 & {12{RWL1[28]}})) |
((mem_13 & {12{RWL1[13]}}) | (mem_29 & {12{RWL1[29]}})) |
((mem_14 & {12{RWL1[14]}}) | (mem_30 & {12{RWL1[30]}})) |
((mem_15 & {12{RWL1[15]}}) | (mem_31 & {12{RWL1[31]}}));

always @(posedge WWL[0]) begin
mem_00 <= ~WBLb;
mem_00 <= WBL | ~WBLb;
end

always @(posedge WWL[1]) begin
mem_01 <= ~WBLb;
mem_01 <= WBL | ~WBLb;
end

always @(posedge WWL[2]) begin
mem_02 <= ~WBLb;
mem_02 <= WBL | ~WBLb;
end

always @(posedge WWL[3]) begin
mem_03 <= ~WBLb;
mem_03 <= WBL | ~WBLb;
end

always @(posedge WWL[4]) begin
mem_04 <= ~WBLb;
mem_04 <= WBL | ~WBLb;
end

always @(posedge WWL[5]) begin
mem_05 <= ~WBLb;
mem_05 <= WBL | ~WBLb;
end

always @(posedge WWL[6]) begin
mem_06 <= ~WBLb;
mem_06 <= WBL | ~WBLb;
end

always @(posedge WWL[7]) begin
mem_07 <= ~WBLb;
mem_07 <= WBL | ~WBLb;
end

always @(posedge WWL[8]) begin
mem_08 <= ~WBLb;
mem_08 <= WBL | ~WBLb;
end

always @(posedge WWL[9]) begin
mem_09 <= ~WBLb;
mem_09 <= WBL | ~WBLb;
end

always @(posedge WWL[10]) begin
mem_10 <= ~WBLb;
mem_10 <= WBL | ~WBLb;
end

always @(posedge WWL[11]) begin
mem_11 <= ~WBLb;
mem_11 <= WBL | ~WBLb;
end

always @(posedge WWL[12]) begin
mem_12 <= ~WBLb;
mem_12 <= WBL | ~WBLb;
end

always @(posedge WWL[13]) begin
mem_13 <= ~WBLb;
mem_13 <= WBL | ~WBLb;
end

always @(posedge WWL[14]) begin
mem_14 <= ~WBLb;
mem_14 <= WBL | ~WBLb;
end

always @(posedge WWL[15]) begin
mem_15 <= ~WBLb;
mem_15 <= WBL | ~WBLb;
end

always @(posedge WWL[16]) begin
mem_16 <= ~WBLb;
mem_16 <= WBL | ~WBLb;
end

always @(posedge WWL[17]) begin
mem_17 <= ~WBLb;
mem_17 <= WBL | ~WBLb;
end

always @(posedge WWL[18]) begin
mem_18 <= ~WBLb;
mem_18 <= WBL | ~WBLb;
end

always @(posedge WWL[19]) begin
mem_19 <= ~WBLb;
mem_19 <= WBL | ~WBLb;
end

always @(posedge WWL[20]) begin
mem_20 <= ~WBLb;
mem_20 <= WBL | ~WBLb;
end

always @(posedge WWL[21]) begin
mem_21 <= ~WBLb;
mem_21 <= WBL | ~WBLb;
end

always @(posedge WWL[22]) begin
mem_22 <= ~WBLb;
mem_22 <= WBL | ~WBLb;
end

always @(posedge WWL[23]) begin
mem_23 <= ~WBLb;
mem_23 <= WBL | ~WBLb;
end

always @(posedge WWL[24]) begin
mem_24 <= ~WBLb;
mem_24 <= WBL | ~WBLb;
end

always @(posedge WWL[25]) begin
mem_25 <= ~WBLb;
mem_25 <= WBL | ~WBLb;
end

always @(posedge WWL[26]) begin
mem_26 <= ~WBLb;
mem_26 <= WBL | ~WBLb;
end

always @(posedge WWL[27]) begin
mem_27 <= ~WBLb;
mem_27 <= WBL | ~WBLb;
end

always @(posedge WWL[28]) begin
mem_28 <= ~WBLb;
mem_28 <= WBL | ~WBLb;
end

always @(posedge WWL[29]) begin
mem_29 <= ~WBLb;
mem_29 <= WBL | ~WBLb;
end

always @(posedge WWL[30]) begin
mem_30 <= ~WBLb;
mem_30 <= WBL | ~WBLb;
end

always @(posedge WWL[31]) begin
mem_31 <= ~WBLb;
mem_31 <= WBL | ~WBLb;
end

// assert errors (multiwrite, etc.)

180
rtl/src/array_shard/regfile_shard_64x24_2r1w_comp.v
Unescape Escape View File

@ -20,10 +20,13 @@

// Behavioral for 64x24 toysram (sdr or ddr), 'shard' (semi-hard)
// 16x12 hard subarrays plus decoder, eval, io comps
// OR
// 32x12 hard subarrays plus decoder, io comps

`timescale 1 ps / 1 ps

module regfile_shard_64x24_2r1w_comp (
module regfile_shard_64x24_2r1w_comp #(
parameter integer RA_32x12 = 1
) (

input rd0_c_na0,
input rd0_c_a0,
@ -228,7 +231,6 @@ wire [0:11] wbl0_b_0x1;
wire [0:11] wbl0_b_1x0;
wire [0:11] wbl0_b_1x1;


// subarray cells; 4x2 16w/12b subarrays
//
// bits are stacked vertically, words horizontally
@ -258,8 +260,15 @@ wire [0:11] wbl0_b_1x1;
// 00x=W0xx0xx 01x=W0xx1xx 10x=W1xx0xx 11x=W1xx1xx (0xx=W0xxxxx, 1xx=W1xxxxx)
// if @3 is final select, subarrays:
// 00x=W0xx0xx 01x=W1xx0xx 10x=W0xx1xx 11x=W1xx1xx (0xx=Wxxx0xx, 1xx=Wxxx1xx)
//
// 32x12 subarrays are L/R pairs and local eval

// subarrays
generate

if (RA_32x12 == 0) begin

toysram_16x12 r000 (
toysram_16x12 r000 (
.RWL0(rwl0_000),
.RWL1(rwl1_000),
.WWL(wwl0_000),
@ -267,8 +276,8 @@ toysram_16x12 r000 (
.RBL1(rbl1_000),
.WBL(wbl0_000),
.WBLb(wbl0_b_000)
);
toysram_16x12 r001 (
);
toysram_16x12 r001 (
.RWL0(rwl0_001),
.RWL1(rwl1_001),
.WWL(wwl0_001),
@ -276,9 +285,9 @@ toysram_16x12 r001 (
.RBL1(rbl1_001),
.WBL(wbl0_001),
.WBLb(wbl0_b_001)
);
);

toysram_16x12 r010 (
toysram_16x12 r010 (
.RWL0(rwl0_010),
.RWL1(rwl1_010),
.WWL(wwl0_010),
@ -286,9 +295,9 @@ toysram_16x12 r010 (
.RBL1(rbl1_010),
.WBL(wbl0_010),
.WBLb(wbl0_b_010)
);
);

toysram_16x12 r011 (
toysram_16x12 r011 (
.RWL0(rwl0_011),
.RWL1(rwl1_011),
.WWL(wwl0_011),
@ -296,9 +305,9 @@ toysram_16x12 r011 (
.RBL1(rbl1_011),
.WBL(wbl0_011),
.WBLb(wbl0_b_011)
);
);

toysram_16x12 r100 (
toysram_16x12 r100 (
.RWL0(rwl0_100),
.RWL1(rwl1_100),
.WWL(wwl0_100),
@ -306,9 +315,9 @@ toysram_16x12 r100 (
.RBL1(rbl1_100),
.WBL(wbl0_100),
.WBLb(wbl0_b_100)
);
);

toysram_16x12 r101 (
toysram_16x12 r101 (
.RWL0(rwl0_101),
.RWL1(rwl1_101),
.WWL(wwl0_101),
@ -316,9 +325,9 @@ toysram_16x12 r101 (
.RBL1(rbl1_101),
.WBL(wbl0_101),
.WBLb(wbl0_b_101)
);
);

toysram_16x12 r110 (
toysram_16x12 r110 (
.RWL0(rwl0_110),
.RWL1(rwl1_110),
.WWL(wwl0_110),
@ -326,9 +335,9 @@ toysram_16x12 r110 (
.RBL1(rbl1_110),
.WBL(wbl0_110),
.WBLb(wbl0_b_110)
);
);

toysram_16x12 r111 (
toysram_16x12 r111 (
.RWL0(rwl0_111),
.RWL1(rwl1_111),
.WWL(wwl0_111),
@ -336,7 +345,55 @@ toysram_16x12 r111 (
.RBL1(rbl1_111),
.WBL(wbl0_111),
.WBLb(wbl0_b_111)
);
);

end else begin

// words 00:31
toysram_32x12 r00 (
.RWL0(rwl0_0x0),
.RWL1(rwl1_0x0),
.WWL(wwl0_0x0),
.RBL0(rbl0_0x0),
.RBL1(rbl1_0x0),
.WBL(wbl0_0x0),
.WBLb(wbl0_b_0x0)
);

toysram_32x12 r01 (
.RWL0(rwl0_0x1),
.RWL1(rwl1_0x1),
.WWL(wwl0_0x1),
.RBL0(rbl0_0x1),
.RBL1(rbl1_0x1),
.WBL(wbl0_0x1),
.WBLb(wbl0_b_0x1)
);

// words 32:47
toysram_32x12 r10 (
.RWL0(rwl0_1x0),
.RWL1(rwl1_1x0),
.WWL(wwl0_1x0),
.RBL0(rbl0_1x0),
.RBL1(rbl1_1x0),
.WBL(wbl0_1x0),
.WBLb(wbl0_b_1x0)
);

// words 48:63
toysram_32x12 r11 (
.RWL0(rwl0_1x1),
.RWL1(rwl1_1x1),
.WWL(wwl0_1x1),
.RBL0(rbl0_1x1),
.RBL1(rbl1_1x1),
.WBL(wbl0_1x1),
.WBLb(wbl0_b_1x1)
);

end
endgenerate

// wordline decodes to one-hots; separate copies for up/down
// separate comps for L/R so i/o macro can divide the center; a3
@ -441,6 +498,10 @@ wordlines_comp_32 dcd_1 (

);

generate

if (RA_32x12 == 0) begin

assign rwl0_000 = rwl0_0x0[0:15];
assign rwl0_001 = rwl0_0x1[0:15];
assign rwl0_010 = rwl0_0x0[16:31];
@ -468,48 +529,52 @@ wordlines_comp_32 dcd_1 (
assign wwl0_110 = wwl0_1x0[16:31];
assign wwl0_111 = wwl0_1x1[16:31];

// local eval

//wtf move to decode!
// precharge repower
// during precharge c_na0 = c_a0 = 0
// 4 copies to 000/010, 001/011, 100/110, 101,111 quads
// rd0
sky130_fd_sc_hd__inv_2 inv0_0x0_b (.A(rd0_c_na0), .Y(pre0_0x0_b));
sky130_fd_sc_hd__inv_2 inv0_0x0 (.A(pre0_0x0_b), .Y(pre0_0x0));
sky130_fd_sc_hd__inv_2 inv0_0x1_b (.A(rd0_c_na0), .Y(pre0_0x1_b));
sky130_fd_sc_hd__inv_2 inv0_0x1 (.A(pre0_0x1_b), .Y(pre0_0x1));
sky130_fd_sc_hd__inv_2 inv0_1x0_b (.A(rd0_c_a0), .Y(pre0_1x0_b));
sky130_fd_sc_hd__inv_2 inv0_1x0 (.A(pre0_1x0_b), .Y(pre0_1x0));
sky130_fd_sc_hd__inv_2 inv0_1x1_b (.A(rd0_c_a0), .Y(pre0_1x1_b));
sky130_fd_sc_hd__inv_2 inv0_1x1 (.A(pre0_1x1_b), .Y(pre0_1x1));
// rd1
sky130_fd_sc_hd__inv_2 inv1_0x0_b (.A(rd0_c_na0), .Y(pre1_0x0_b));
sky130_fd_sc_hd__inv_2 inv1_0x0 (.A(pre1_0x0_b), .Y(pre1_0x0));
sky130_fd_sc_hd__inv_2 inv1_0x1_b (.A(rd0_c_na0), .Y(pre1_0x1_b));
sky130_fd_sc_hd__inv_2 inv1_0x1 (.A(pre1_0x1_b), .Y(pre1_0x1));
sky130_fd_sc_hd__inv_2 inv1_1x0_b (.A(rd0_c_a0), .Y(pre1_1x0_b));
sky130_fd_sc_hd__inv_2 inv1_1x0 (.A(pre1_1x0_b), .Y(pre1_1x0));
sky130_fd_sc_hd__inv_2 inv1_1x1_b (.A(rd0_c_a0), .Y(pre1_1x1_b));
sky130_fd_sc_hd__inv_2 inv1_1x1 (.A(pre1_1x1_b), .Y(pre1_1x1));

// quad local evals, 2 ports
local_eval_comp eval_0x0 (
// local eval

//wtf move to decode!
// precharge repower
// during precharge c_na0 = c_a0 = 0
// 4 copies to 000/010, 001/011, 100/110, 101,111 quads
// rd0
sky130_fd_sc_hd__inv_2 inv0_0x0_b (.A(rd0_c_na0), .Y(pre0_0x0_b));
sky130_fd_sc_hd__inv_2 inv0_0x0 (.A(pre0_0x0_b), .Y(pre0_0x0));
sky130_fd_sc_hd__inv_2 inv0_0x1_b (.A(rd0_c_na0), .Y(pre0_0x1_b));
sky130_fd_sc_hd__inv_2 inv0_0x1 (.A(pre0_0x1_b), .Y(pre0_0x1));
sky130_fd_sc_hd__inv_2 inv0_1x0_b (.A(rd0_c_a0), .Y(pre0_1x0_b));
sky130_fd_sc_hd__inv_2 inv0_1x0 (.A(pre0_1x0_b), .Y(pre0_1x0));
sky130_fd_sc_hd__inv_2 inv0_1x1_b (.A(rd0_c_a0), .Y(pre0_1x1_b));
sky130_fd_sc_hd__inv_2 inv0_1x1 (.A(pre0_1x1_b), .Y(pre0_1x1));
// rd1
sky130_fd_sc_hd__inv_2 inv1_0x0_b (.A(rd0_c_na0), .Y(pre1_0x0_b));
sky130_fd_sc_hd__inv_2 inv1_0x0 (.A(pre1_0x0_b), .Y(pre1_0x0));
sky130_fd_sc_hd__inv_2 inv1_0x1_b (.A(rd0_c_na0), .Y(pre1_0x1_b));
sky130_fd_sc_hd__inv_2 inv1_0x1 (.A(pre1_0x1_b), .Y(pre1_0x1));
sky130_fd_sc_hd__inv_2 inv1_1x0_b (.A(rd0_c_a0), .Y(pre1_1x0_b));
sky130_fd_sc_hd__inv_2 inv1_1x0 (.A(pre1_1x0_b), .Y(pre1_1x0));
sky130_fd_sc_hd__inv_2 inv1_1x1_b (.A(rd0_c_a0), .Y(pre1_1x1_b));
sky130_fd_sc_hd__inv_2 inv1_1x1 (.A(pre1_1x1_b), .Y(pre1_1x1));

// quad local evals, 2 ports
local_eval_comp eval_0x0 (
.PRE0_b(pre0_0x0), .RBL0_L(rbl0_000), .RBL0_R(rbl0_010), .RBL0_O_b(rbl0_0x0),
.PRE1_b(pre1_0x0), .RBL1_L(rbl1_000), .RBL1_R(rbl1_010), .RBL1_O_b(rbl1_0x0)
);
local_eval_comp eval_0x1 (
);
local_eval_comp eval_0x1 (
.PRE0_b(pre0_0x1), .RBL0_L(rbl0_001), .RBL0_R(rbl0_011), .RBL0_O_b(rbl0_0x1),
.PRE1_b(pre1_0x1), .RBL1_L(rbl1_001), .RBL1_R(rbl1_011), .RBL1_O_b(rbl1_0x1)
);
local_eval_comp eval_1x0 (
);
local_eval_comp eval_1x0 (
.PRE0_b(pre0_1x0), .RBL0_L(rbl0_100), .RBL0_R(rbl0_110), .RBL0_O_b(rbl0_1x0),
.PRE1_b(pre1_1x0), .RBL1_L(rbl1_100), .RBL1_R(rbl1_110), .RBL1_O_b(rbl1_1x0)
);
local_eval_comp eval_1x1 (
);
local_eval_comp eval_1x1 (
.PRE0_b(pre0_1x1), .RBL0_L(rbl0_101), .RBL0_R(rbl0_111), .RBL0_O_b(rbl0_1x1),
.PRE1_b(pre1_1x1), .RBL1_L(rbl1_101), .RBL1_R(rbl1_111), .RBL1_O_b(rbl1_1x1)
);
);

end

endgenerate

// separate ports by quads for placement
// address passes through - should start decode here
@ -620,6 +685,15 @@ inout_comp io (

);

assign wbl0_000 = wbl0_0x0;
assign wbl0_001 = wbl0_0x1;
assign wbl0_010 = wbl0_0x0;
assign wbl0_011 = wbl0_0x1;
assign wbl0_100 = wbl0_1x0;
assign wbl0_101 = wbl0_0x1;
assign wbl0_110 = wbl0_1x0;
assign wbl0_111 = wbl0_0x1;

assign wbl0_b_000 = wbl0_b_0x0;
assign wbl0_b_001 = wbl0_b_0x1;
assign wbl0_b_010 = wbl0_b_0x0;

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