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toy-sram
mirror of https://github.com/OpenPOWERFoundation/toy-sram
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custom junk and site verif from mpw7

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master
openpowerwtf 2 years ago
parent d5fc9bcd00
commit 685d4a98c4
54 changed files with 34463 additions and 74 deletions
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125
custom/gds.py
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#!/usr/bin/python

from optparse import OptionParser
import gdspy


usage = '%prog [options] inFile'
parser = OptionParser(usage=usage)
(options, args) = parser.parse_args()

if len(args) != 1:
parser.error('Input .gds required.')

inFile = args[0]



gdsii = gdspy.GdsLibrary()
gdsii.read_gds(inFile)

# list of unreferenced cells
c = gdsii.top_level()
print(c)

LayerNames = {
'64:5' : 'nwell, label',
'64:59' : 'pwell, label',
'67:5' : 'li1, label',
'68:5' : 'met1, label',
'83:44' : 'text, label'
}

class Polygon:
def __init__(self, polygon, layer, datatype, properties=None):
self.polygon = polygon
self.layer = layer
self.datatype = datatype
self.properties = properties

class PolygonSets:
def __init__(self, properties):
self.polygons = []
self.properties = properties

maxLayers = 300
maxTypes = 300

numLabels = 0
numPolygons = 0
numPolygonSets = 0

# layer/type
labels = []
for i in range(maxLayers):
labels.append([])
for j in range(maxTypes):
labels[i].append([])

polygons = []
for i in range(maxLayers):
polygons.append([])
for j in range(maxTypes):
polygons[i].append([])

for i in range(len(c)):

b = c[i].get_bounding_box()
print(f'Cell {i} {b}')

p = c[i].get_dependencies()
print(f'Dependencies ({len(p)})')
for pp in p:
print(p)

p = c[i].get_paths()
print(f'Paths ({len(p)})')
for pp in p:
print(pp)

p = c[i].get_labels()
#print(f'Labels ({len(p)})')
for pp in p:
labels[pp.layer][pp.texttype].append(pp)
numLabels += 1

#p = c[i].get_datatypes()
#print(f'Data Types ({len(p)})')
#for pp in p:
# print(pp)

# print(f'Text Types')
# bug in source
# texttypes.update(reference.ref_cell.get_textypes())
# for l in c[i].get_texttypes():
# print(l)

#p = c[i].get_layers()
#print(f'Layers ({len(p)})')
#p = c[i].get_polygons()
#print(f'Polygons ({len(p)})')

# keep these as polygonsets? pp.properties belongs to the set only
p = c[i].get_polygonsets()
print(f'Polygon Sets ({len(p)})')
for pp in p:
for i in range(len(pp.polygons)):
numPolygons += 1
polygons[pp.layers[i]][pp.datatypes[i]].append(
Polygon(pp.polygons[i], pp.layers[i], pp.datatypes[i])
)
numPolygonSets += 1


print(f' Labels: {numLabels}')
print(f' Polygons: {numPolygons}')
print(f'PolygonSets: {numPolygonSets}')

for i in range(maxLayers):
for j in range(maxTypes):
if (len(labels[i][j]) > 0):
name = LayerNames[f'{i}:{j}']
print(f'{i:3d}:{j:3d} {name}')
for k in range(len(labels[i][j])):
label = labels[i][j][k]
print(f' {label.text} {label.position}')

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custom/klayout/lef
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toysram_local_eval.lef: NOWIREEXTENSIONATPIN ON ;
toysram_local_eval.lef: PIN RBL_O
toysram_local_eval.lef: PIN PRE_R_b
toysram_local_eval.lef: PIN VPB
toysram_local_eval.lef: PIN VNB
toysram_local_eval.lef: PIN VPWR

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custom/klayout/magic.tcl
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# magic -rcfile magic.tcl

source ../magic/.magic_tech/.magicrc

gds read local_eval.gds
load toysram_local_eval

# for some reason these don't return values; just puts
drc catchup
drc statistics
drc count total

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custom/klayout/magic_pullup.tcl
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# magic -rcfile magic.tcl

source ../magic/.magic_tech/.magicrc

gds read toysram_local_pullup.gds
load toysram_local_pullup

# for some reason these don't return values; just puts
drc catchup
drc statistics
drc count total

20
custom/klayout/magicdrc.tcl
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# magic -dnull -noconsole -rcfile magicdrc.tcl local_eval.gds

source ../magic/.magic_tech/.magicrc
#sleep 10

gds read local_eval.gds
load toysram_local_eval

# for some reason these don't return values; just puts
drc catchup
drc statistics
drc count total

drc find 1
drc find 2
drc find 3
drc find 4
drc find 5

exit

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custom/klayout/magicdrc_pullup.tcl
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# magic -dnull -noconsole -rcfile magicdrc_pullup.tcl toysram_local_pullup.gds

source ../magic/.magic_tech/.magicrc
#sleep 10

gds read toysram_local_pullup.gds
load toysram_local_pullup

# for some reason these don't return values; just puts
drc catchup
drc statistics
drc count total

drc find 1
drc find 2
drc find 3
drc find 4
drc find 5

exit

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custom/klayout/sky130_fd_sc_hd__nand2_1.gds
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custom/klayout/sky130_fd_sc_hd__nand2_1.lef
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VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO sky130_fd_sc_hd__nand2_1
CLASS CORE ;
FOREIGN sky130_fd_sc_hd__nand2_1 ;
ORIGIN 0.000 0.000 ;
SIZE 1.380 BY 2.720 ;
SYMMETRY X Y R90 ;
SITE unithd ;
PIN A
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.247500 ;
PORT
LAYER li1 ;
RECT 0.940 1.075 1.275 1.325 ;
END
END A
PIN B
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.247500 ;
PORT
LAYER li1 ;
RECT 0.095 1.055 0.430 1.325 ;
END
END B
PIN VGND
DIRECTION INOUT ;
USE GROUND ;
SHAPE ABUTMENT ;
PORT
LAYER li1 ;
RECT 0.085 0.085 0.395 0.885 ;
RECT 0.000 -0.085 1.380 0.085 ;
LAYER mcon ;
RECT 0.145 -0.085 0.315 0.085 ;
RECT 0.605 -0.085 0.775 0.085 ;
RECT 1.065 -0.085 1.235 0.085 ;
LAYER met1 ;
RECT 0.000 -0.240 1.380 0.240 ;
END
END VGND
PIN VNB
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER pwell ;
RECT 0.025 0.105 1.375 1.015 ;
RECT 0.140 -0.085 0.310 0.105 ;
END
END VNB
PIN VPB
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER nwell ;
RECT -0.190 1.305 1.570 2.910 ;
END
END VPB
PIN VPWR
DIRECTION INOUT ;
USE POWER ;
SHAPE ABUTMENT ;
PORT
LAYER li1 ;
RECT 0.000 2.635 1.380 2.805 ;
RECT 0.085 1.495 0.365 2.635 ;
RECT 1.035 1.495 1.295 2.635 ;
LAYER mcon ;
RECT 0.145 2.635 0.315 2.805 ;
RECT 0.605 2.635 0.775 2.805 ;
RECT 1.065 2.635 1.235 2.805 ;
LAYER met1 ;
RECT 0.000 2.480 1.380 2.960 ;
END
END VPWR
PIN Y
DIRECTION OUTPUT ;
USE SIGNAL ;
ANTENNADIFFAREA 0.439000 ;
PORT
LAYER li1 ;
RECT 0.535 1.485 0.865 2.465 ;
RECT 0.600 0.885 0.770 1.485 ;
RECT 0.600 0.255 1.295 0.885 ;
END
END Y
END sky130_fd_sc_hd__nand2_1
END LIBRARY

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custom/klayout/toysram_local_eval.lef
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VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO toysram_local_eval
CLASS BLOCK ;
FOREIGN toysram_local_eval ;
ORIGIN 0.270 0.150 ;
SIZE 2.440 BY 3.200 ;
PIN RBL_O
ANTENNAGATEAREA 0.555000 ;
ANTENNADIFFAREA 0.898275 ;
PORT
LAYER li1 ;
RECT 0.455 1.575 0.835 2.555 ;
RECT 0.015 1.190 0.350 1.415 ;
RECT 0.570 1.190 0.740 1.575 ;
RECT 1.580 1.415 1.825 2.525 ;
RECT 0.910 1.190 1.825 1.415 ;
RECT 0.015 1.165 1.825 1.190 ;
RECT 0.015 1.145 1.245 1.165 ;
RECT 0.170 0.975 1.245 1.145 ;
RECT 0.005 0.345 1.315 0.975 ;
RECT 0.005 0.175 1.245 0.345 ;
RECT -0.080 0.005 1.760 0.175 ;
LAYER mcon ;
RECT 0.065 0.005 0.235 0.175 ;
RECT 0.525 0.005 0.695 0.175 ;
RECT 0.985 0.005 1.155 0.175 ;
RECT 1.445 0.005 1.615 0.175 ;
LAYER met1 ;
RECT -0.080 -0.150 1.875 0.330 ;
END
END RBL_O
PIN PRE_R_b
ANTENNAGATEAREA 0.116025 ;
PORT
LAYER li1 ;
RECT 1.495 0.585 1.830 0.855 ;
END
END PRE_R_b
PIN VPB
PORT
LAYER nwell ;
RECT -0.270 1.395 2.170 3.000 ;
END
END VPB
PIN VNB
PORT
LAYER pwell ;
RECT -0.055 0.195 1.395 1.105 ;
RECT 0.060 0.005 0.230 0.195 ;
END
END VNB
PIN VPWR
USE POWER ;
PORT
LAYER li1 ;
RECT -0.080 2.725 1.760 2.895 ;
RECT 0.005 1.585 0.285 2.725 ;
RECT 1.055 1.585 1.315 2.725 ;
LAYER mcon ;
RECT 0.065 2.725 0.235 2.895 ;
RECT 0.525 2.725 0.695 2.895 ;
RECT 0.985 2.725 1.155 2.895 ;
RECT 1.445 2.725 1.615 2.895 ;
LAYER met1 ;
RECT -0.080 2.570 1.880 3.050 ;
END
END VPWR
END toysram_local_eval
END LIBRARY

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custom/klayout/toysram_local_pullup.lef
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VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO toysram_local_pullup
CLASS BLOCK ;
FOREIGN toysram_local_pullup ;
ORIGIN 0.000 0.000 ;
SIZE 1.380 BY 2.720 ;
PIN RBL
ANTENNADIFFAREA 0.260000 ;
PORT
LAYER li1 ;
RECT 0.720 1.485 1.050 2.465 ;
RECT 0.820 0.990 1.050 1.485 ;
END
END RBL
PIN PRE_b
ANTENNAGATEAREA 0.150000 ;
PORT
LAYER li1 ;
RECT 0.320 1.075 0.650 1.315 ;
END
END PRE_b
PIN VPB
PORT
LAYER nwell ;
RECT -0.190 1.305 1.570 2.910 ;
END
END VPB
PIN VGND
USE GROUND ;
PORT
LAYER li1 ;
RECT 0.000 -0.085 1.380 0.085 ;
LAYER mcon ;
RECT 0.145 -0.085 0.315 0.085 ;
RECT 0.605 -0.085 0.775 0.085 ;
RECT 1.065 -0.085 1.235 0.085 ;
LAYER met1 ;
RECT 0.000 -0.240 1.380 0.240 ;
END
END VGND
PIN VPWR
USE POWER ;
PORT
LAYER li1 ;
RECT 0.000 2.635 1.380 2.805 ;
RECT 0.340 1.495 0.550 2.635 ;
LAYER mcon ;
RECT 0.145 2.635 0.315 2.805 ;
RECT 0.605 2.635 0.775 2.805 ;
RECT 1.065 2.635 1.235 2.805 ;
LAYER met1 ;
RECT 0.000 2.480 1.380 2.960 ;
END
END VPWR
END toysram_local_pullup
END LIBRARY

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55
custom/magic/.magic_tech/.magicrc
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### Process this file with the m4 processor
###

if {[info exists ::env(PDK_ROOT)]} {
set PDK_ROOT $::env(PDK_ROOT)
} else {
shell echo "PDK_ROOT must be set!"
quit
}

# MUST CHANGE THIS TO REPOSITORIES TOP LEVEL DIRECTORY
set PDK_ROOT /path/to/osu-toy-sram
set TECH_ROOT ${PDK_ROOT}/sky130B/libs.tech/magic/*.magicrc
set rc [glob -nocomplain $TECH_ROOT]
if {[llength $rc] != 1} {
shell echo "Expected one .magicrc file in $TECH_ROOT. Found:"
shell echo $rc
quit
}

puts "Sourcing $rc..."
source $rc

puts stdout "Sourcing design .magicrc for technology sky130 ..."

# MUST CHANGE THIS TO REPOSITORIES TOP LEVEL DIRECTORY
#set PDK_ROOT /path/to/osu-toy-sram

#puts stdout "Sourcing design .magicrc for technology sky130 ..."

# Put grid on 0.005 pitch. This is important, as some commands don't
# rescale the grid automatically (such as lef read?).

set scalefac [tech lambda]
if {[lindex $scalefac 1] < 2} {
scalegrid 1 2
}
#set scalefac [tech lambda]
#if {[lindex $scalefac 1] < 2} {
# scalegrid 1 2
#}

# drc off
drc euclidean on
#drc euclidean on

# Change this to a fixed number for repeatable behavior with GDS writes
# e.g., "random seed 12345"
catch {random seed}
#catch {random seed}

# Turn off the scale option on ext2spice or else it conflicts with the
# scale in the model files.
ext2spice scale off
#ext2spice scale off


# Set this to the folder that holds the technology files
set TECH_ROOT ${PDK_ROOT}/magic/.magic_tech
#set TECH_ROOT ${PDK_ROOT}/magic/.magic_tech

# loading technology
tech load ${TECH_ROOT}/sky130A.tech
#tech load ${TECH_ROOT}/sky130A.tech
# load device generator
#source $TECH_ROOT/sky130.tcl

# load bind keys (optional)
source ${TECH_ROOT}/sky130.BindKeys
#source ${TECH_ROOT}/sky130.BindKeys

# set units to lambda grid
snap internal
#snap internal

# set sky130 standard power, ground, and substrate names
set VDD VPWR
set GND VGND
set SUB VSUBS
#set VDD VPWR
#set GND VGND
#set SUB VSUBS

# add path to IP from catalog. This procedure defined in the PDK script.
catch {magic::query_mylib_ip}
#catch {magic::query_mylib_ip}
# add path to local IP from user design space. Defined in the PDK script.
catch {magic::query_my_projects}
#catch {magic::query_my_projects}

# Custom macros
#macro XK_Left "scroll l .1 w"

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custom/magic/10T_16x8_magic.lef
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custom/magic/10T_toy_magic.lef
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VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO 10T_toy_magic
CLASS BLOCK ;
FOREIGN 10T_toy_magic ;
ORIGIN 0.500 0.095 ;
SIZE 2.760 BY 1.350 ;
PIN RWL
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.031500 ;
PORT
LAYER li1 ;
RECT 1.895 0.415 2.045 0.585 ;
END
END RWL
PIN RWL
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.031500 ;
PORT
LAYER li1 ;
RECT -0.285 0.415 -0.135 0.585 ;
END
END RWL
PIN WBL
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNADIFFAREA 0.024175 ;
PORT
LAYER li1 ;
RECT 1.820 0.825 1.895 0.970 ;
END
END WBL
PIN WBLb
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNADIFFAREA 0.023100 ;
PORT
LAYER li1 ;
RECT -0.130 0.825 -0.055 0.965 ;
END
END WBLb
PIN RBL0
DIRECTION OUTPUT ;
USE SIGNAL ;
ANTENNADIFFAREA 0.045150 ;
PORT
LAYER li1 ;
RECT 2.185 0.095 2.260 0.305 ;
END
END RBL0
PIN RBL1
DIRECTION OUTPUT ;
USE SIGNAL ;
ANTENNADIFFAREA 0.045150 ;
PORT
LAYER li1 ;
RECT -0.500 0.095 -0.425 0.305 ;
END
END RBL1
PIN VDD
DIRECTION INOUT ;
USE POWER ;
SHAPE ABUTMENT ;
PORT
LAYER nwell ;
RECT 0.490 0.625 1.255 1.105 ;
LAYER li1 ;
RECT 0.800 1.035 0.960 1.105 ;
RECT 0.810 1.025 0.950 1.035 ;
LAYER met1 ;
RECT -0.500 1.035 2.260 1.105 ;
END
END VDD
PIN GND
DIRECTION INOUT ;
USE GROUND ;
SHAPE ABUTMENT ;
PORT
LAYER pwell ;
RECT -0.500 0.395 0.350 1.255 ;
RECT 1.410 0.395 2.260 1.255 ;
RECT -0.500 -0.095 2.260 0.395 ;
LAYER li1 ;
RECT 0.810 -0.025 0.950 -0.015 ;
RECT 0.800 -0.095 0.960 -0.025 ;
LAYER met1 ;
RECT -0.500 -0.095 2.260 -0.025 ;
END
END GND
OBS
LAYER li1 ;
RECT 0.275 0.825 0.350 0.965 ;
RECT 0.490 0.775 0.565 0.915 ;
RECT 1.195 0.835 1.255 0.915 ;
POLYGON 1.195 0.835 1.255 0.835 1.255 0.775 ;
RECT 1.410 0.825 1.485 0.965 ;
RECT 0.220 0.305 0.370 0.475 ;
RECT 0.610 0.440 0.760 0.610 ;
RECT 1.000 0.440 1.150 0.610 ;
RECT 1.390 0.305 1.540 0.475 ;
RECT 0.485 0.220 0.535 0.255 ;
POLYGON 0.535 0.255 0.570 0.220 0.535 0.220 ;
RECT 0.485 0.095 0.570 0.220 ;
RECT 1.190 0.095 1.275 0.255 ;
END
END 10T_toy_magic
END LIBRARY

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custom/magic/local_eval.lef
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VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
PROPERTYDEFINITIONS
MACRO maskLayoutSubType STRING ;
MACRO prCellType STRING ;
MACRO originalViewName STRING ;
END PROPERTYDEFINITIONS

MACRO sky130_fd_sc_hdll__nand2_1
CLASS CORE ;
FOREIGN sky130_fd_sc_hdll__nand2_1 ;
ORIGIN 0.000 0.000 ;
SIZE 1.840 BY 2.720 ;
SYMMETRY X Y R90 ;
SITE unithd ;
PIN A
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.277500 ;
PORT
LAYER li1 ;
RECT 0.990 1.075 1.375 1.325 ;
END
END A
PIN B
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.277500 ;
PORT
LAYER li1 ;
RECT 0.095 1.055 0.430 1.325 ;
END
END B
PIN VGND
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER li1 ;
RECT 0.085 0.085 0.395 0.885 ;
RECT 0.000 -0.085 1.840 0.085 ;
LAYER mcon ;
RECT 0.145 -0.085 0.315 0.085 ;
RECT 0.605 -0.085 0.775 0.085 ;
RECT 1.065 -0.085 1.235 0.085 ;
RECT 1.525 -0.085 1.695 0.085 ;
LAYER met1 ;
RECT 0.000 -0.240 1.840 0.240 ;
END
END VGND
PIN VNB
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER pwell ;
RECT 0.025 0.105 1.475 1.015 ;
RECT 0.140 -0.085 0.310 0.105 ;
END
END VNB
PIN VPB
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER nwell ;
RECT -0.190 1.305 2.030 2.910 ;
END
END VPB
PIN VPWR
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER li1 ;
RECT 0.000 2.635 1.840 2.805 ;
RECT 0.085 1.495 0.365 2.635 ;
RECT 1.135 1.495 1.395 2.635 ;
LAYER mcon ;
RECT 0.145 2.635 0.315 2.805 ;
RECT 0.605 2.635 0.775 2.805 ;
RECT 1.065 2.635 1.235 2.805 ;
RECT 1.525 2.635 1.695 2.805 ;
LAYER met1 ;
RECT 0.000 2.480 1.840 2.960 ;
END
END VPWR
PIN Y
DIRECTION OUTPUT ;
USE SIGNAL ;
ANTENNADIFFAREA 0.491500 ;
PORT
LAYER li1 ;
RECT 0.535 1.485 0.915 2.465 ;
RECT 0.650 0.885 0.820 1.485 ;
RECT 0.650 0.255 1.395 0.885 ;
END
END Y
PROPERTY maskLayoutSubType "abstract" ;
PROPERTY prCellType "standard" ;
PROPERTY originalViewName "layout" ;
END sky130_fd_sc_hdll__nand2_1
MACRO local_eval
CLASS BLOCK ;
FOREIGN local_eval ;
ORIGIN 0.270 0.150 ;
SIZE 2.220 BY 3.200 ;
OBS
LAYER nwell ;
RECT -0.270 1.395 1.950 3.000 ;
LAYER pwell ;
RECT -0.055 0.195 1.395 1.105 ;
RECT 0.060 0.005 0.230 0.195 ;
LAYER li1 ;
RECT -0.080 2.725 1.760 2.895 ;
RECT 0.005 1.585 0.285 2.725 ;
RECT 0.455 1.575 0.835 2.555 ;
RECT 1.055 1.585 1.315 2.725 ;
RECT 0.015 1.145 0.350 1.415 ;
RECT 0.570 0.975 0.740 1.575 ;
RECT 0.910 1.165 1.295 1.415 ;
RECT 0.005 0.175 0.315 0.975 ;
RECT 0.570 0.345 1.315 0.975 ;
RECT -0.080 0.005 1.760 0.175 ;
LAYER mcon ;
RECT 0.065 2.725 0.235 2.895 ;
RECT 0.525 2.725 0.695 2.895 ;
RECT 0.985 2.725 1.155 2.895 ;
RECT 1.445 2.725 1.615 2.895 ;
RECT 0.065 0.005 0.235 0.175 ;
RECT 0.525 0.005 0.695 0.175 ;
RECT 0.985 0.005 1.155 0.175 ;
RECT 1.445 0.005 1.615 0.175 ;
LAYER met1 ;
RECT -0.080 2.570 1.760 3.050 ;
RECT -0.080 -0.150 1.760 0.330 ;
END
END local_eval
END LIBRARY

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custom/magic/local_eval.mag
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magic
tech sky130B
timestamp 1667750849
use sky130_fd_sc_hdll__nand2_1 sky130_fd_sc_hdll__nand2_1_0 $PDKPATH/libs.ref/sky130_fd_sc_hdll/mag
timestamp 1667402666
transform 1 0 -8 0 1 9
box -19 -24 203 296
<< end >>

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custom/magic/nand2_1.gds
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custom/magic/nand2_1.mag
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magic
tech sky130B
timestamp 1667750849
use sky130_fd_sc_hdll__nand2_1 sky130_fd_sc_hdll__nand2_1_0 $PDKPATH/libs.ref/sky130_fd_sc_hdll/mag
timestamp 1667402666
transform 1 0 -8 0 1 9
box -19 -24 203 296
<< end >>

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custom/magic/sky130_fd_pr__rf_pfet_01v8_aF02W0p84L0p15.gds
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custom/magic/sky130_fd_sc_hd__inv_1.gds
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custom/magic/sky130_fd_sc_hd__inv_1.lef
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VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO sky130_fd_sc_hd__inv_1
CLASS BLOCK ;
FOREIGN sky130_fd_sc_hd__inv_1 ;
ORIGIN 0.000 0.000 ;
SIZE 1.380 BY 2.720 ;
PIN Y
ANTENNADIFFAREA 0.429000 ;
PORT
LAYER li1 ;
RECT 0.720 1.485 1.050 2.465 ;
RECT 0.820 0.885 1.050 1.485 ;
RECT 0.720 0.255 1.050 0.885 ;
END
END Y
PIN A
ANTENNAGATEAREA 0.247500 ;
PORT
LAYER li1 ;
RECT 0.320 1.075 0.650 1.315 ;
END
END A
PIN VPB
PORT
LAYER nwell ;
RECT -0.190 1.305 1.570 2.910 ;
END
END VPB
PIN VNB
PORT
LAYER pwell ;
RECT 0.210 0.105 1.140 1.015 ;
RECT 0.210 0.085 0.315 0.105 ;
RECT 0.145 -0.085 0.315 0.085 ;
END
END VNB
PIN VGND
USE GROUND ;
PORT
LAYER li1 ;
RECT 0.320 0.085 0.550 0.905 ;
RECT 0.000 -0.085 1.380 0.085 ;
LAYER mcon ;
RECT 0.145 -0.085 0.315 0.085 ;
RECT 0.605 -0.085 0.775 0.085 ;
RECT 1.065 -0.085 1.235 0.085 ;
LAYER met1 ;
RECT 0.000 -0.240 1.380 0.240 ;
END
END VGND
PIN VPWR
USE POWER ;
PORT
LAYER li1 ;
RECT 0.000 2.635 1.380 2.805 ;
RECT 0.340 1.495 0.550 2.635 ;
LAYER mcon ;
RECT 0.145 2.635 0.315 2.805 ;
RECT 0.605 2.635 0.775 2.805 ;
RECT 1.065 2.635 1.235 2.805 ;
LAYER met1 ;
RECT 0.000 2.480 1.380 2.960 ;
END
END VPWR
END sky130_fd_sc_hd__inv_1
END LIBRARY

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custom/magic/sky130_fd_sc_hdll__nand2_1.lef
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VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO sky130_fd_sc_hdll__nand2_1
CLASS BLOCK ;
FOREIGN sky130_fd_sc_hdll__nand2_1 ;
ORIGIN 0.000 0.000 ;
SIZE 1.840 BY 2.720 ;
PIN Y
ANTENNADIFFAREA 0.491500 ;
PORT
LAYER li1 ;
RECT 0.535 1.485 0.915 2.465 ;
RECT 0.650 0.885 0.820 1.485 ;
RECT 0.650 0.255 1.395 0.885 ;
END
END Y
PIN B
ANTENNAGATEAREA 0.277500 ;
PORT
LAYER li1 ;
RECT 0.095 1.055 0.430 1.325 ;
END
END B
PIN A
ANTENNAGATEAREA 0.277500 ;
PORT
LAYER li1 ;
RECT 0.990 1.075 1.375 1.325 ;
END
END A
PIN VPB
PORT
LAYER nwell ;
RECT -0.190 1.305 2.030 2.910 ;
END
END VPB
PIN VNB
PORT
LAYER pwell ;
RECT 0.025 0.105 1.475 1.015 ;
RECT 0.140 -0.085 0.310 0.105 ;
END
END VNB
PIN VGND
USE GROUND ;
PORT
LAYER li1 ;
RECT 0.085 0.085 0.395 0.885 ;
RECT 0.000 -0.085 1.840 0.085 ;
LAYER mcon ;
RECT 0.145 -0.085 0.315 0.085 ;
RECT 0.605 -0.085 0.775 0.085 ;
RECT 1.065 -0.085 1.235 0.085 ;
RECT 1.525 -0.085 1.695 0.085 ;
LAYER met1 ;
RECT 0.000 -0.240 1.840 0.240 ;
END
END VGND
PIN VPWR
USE POWER ;
PORT
LAYER li1 ;
RECT 0.000 2.635 1.840 2.805 ;
RECT 0.085 1.495 0.365 2.635 ;
RECT 1.135 1.495 1.395 2.635 ;
LAYER mcon ;
RECT 0.145 2.635 0.315 2.805 ;
RECT 0.605 2.635 0.775 2.805 ;
RECT 1.065 2.635 1.235 2.805 ;
RECT 1.525 2.635 1.695 2.805 ;
LAYER met1 ;
RECT 0.000 2.480 1.840 2.960 ;
END
END VPWR
END sky130_fd_sc_hdll__nand2_1
END LIBRARY

494
custom/magic/tmp.txt
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[<gdspy.library.Cell object at 0x7f228c1e3fa0>]
Cell 0 [[-0.27 -0.15]
[ 1.95 3.05]]
Dependencies (1)
{<gdspy.library.Cell object at 0x7f228e0f0a60>}
Paths (0)
Labels (10)
Label ("Y", at (0.6050000000000001, 1.655), rotation None, magnification 0.125, reflection False, layer 67, texttype 5)
Label ("Y", at (0.6050000000000001, 1.995), rotation None, magnification 0.125, reflection False, layer 67, texttype 5)
Label ("Y", at (1.045, 0.87), rotation None, magnification 0.125, reflection False, layer 67, texttype 5)
Label ("B", at (0.14500000000000002, 1.28), rotation None, magnification 0.125, reflection False, layer 67, texttype 5)
Label ("A", at (1.065, 1.28), rotation None, magnification 0.125, reflection False, layer 67, texttype 5)
Label ("VPB", at (0.14500000000000002, 2.81), rotation None, magnification 0.1, reflection False, layer 64, texttype 5)
Label ("VNB", at (0.14500000000000002, 0.09), rotation None, magnification 0.1, reflection False, layer 64, texttype 59)
Label ("VGND", at (0.15000000000000002, 0.09), rotation None, magnification 0.1, reflection False, layer 68, texttype 5)
Label ("VPWR", at (0.14500000000000002, 2.81), rotation None, magnification 0.1, reflection False, layer 68, texttype 5)
Label ("nand2_1", at (-0.08, 0.09), rotation 90.0, magnification 0.1, reflection False, layer 83, texttype 44)
Data Types (5)
0
16
4
20
44
Layers (13)
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[[-0.08 1.065]
[ 1.76 1.065]
[ 1.76 1.435]
[-0.08 1.435]]

172
custom/magic/wtf-Bindkeys
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#
# Cadence-compatibility bindings except where marked.
#
macro f "view" ;# zoom to fit window
macro ^z "zoom 0.5" ;# zoom in
macro Z "zoom 2" ;# zoom out
macro B "popstack" ;# up hierarchy
macro X {pushstack [cellname list self]} ;# down hierarchy
macro x "edit" ;# down hierarchy, edit-in-place
macro b "select top cell ; edit" ;# up hierarchy from edit-in-place
macro p "tool wire; magic::trackwire %W pick" ;# path
macro ^r "redraw"
macro ^f "unexpand"
macro F "expand"
macro ^a "select area"
macro ^d "select clear"
macro k "magic::measure"
macro K "magic::unmeasure"
macro i "magic::promptload getcell"
macro l "magic::update_texthelper ; wm deiconify .texthelper ; raise .texthelper"
macro O "magic::clock"
macro <del> "magic::delete"

# Toolkit parameter dialog
macro q "magic::gencell {} ; raise .params"
#
# The following should be already implemented as existing Magic bindings
#
macro u "undo"
macro U "redo"
macro m "move"
macro c "copy"
#
# Compatibility with Electric; Cadence bindings are on function keys and
# do not work through the VNC.
macro ^s "magic::promptsave magic" ;# save dialog menu

#
# Bertrand's bindings follow except where marked.
#
macro < sideways
macro ^ upsidedown
#
# Set grid at 1 micron
#
macro 0 "grid on ; grid 1l" ;# Grid at 0.5um (1 lambda)
# macro ^f "feedback clear" ;# conflicts with Cadence binding
#
# Paint/Erase macros
#
macro 1 "paint m1"
macro ! "erase m1"
macro 2 "paint m2"
macro @ "erase m2"
macro 3 "paint m3"
macro # "erase m3"
macro 4 "paint m4"
macro $ "erase m4"
macro 5 "paint mtp"
macro % "erase mtp"

macro 7 "paint poly"
# macro & "erase poly"
# macro p "paint pdiff"
macro n "paint ndiff"
# macro l "erase labels"
macro P "erase pdiff"
macro N "erase ndiff"
macro y "drc check; drc why"
macro ? "select area; what"

macro / "expand toggle"
macro ^w "writeall force"
macro ^e "edit"
# macro ^x "quit"

macro z "findbox zoom"
# "f" conflicts with Cadence "full view", so use control-i to select cells.
# macro f "select cell"
macro ^i "select cell"

# Leave keypad bindings as-is, further down. However, keypad
# keys generally don't translate through the VNC session, so
# use the following arrow key bindings:
#
# no shift shift
# arrows only -> Pan 10% 100%
# with alt -> Move 1 lambda 1 grid
# with ctrl -> Stretch 1 lambda 1 grid
#
# Pan 10 percent of the window size with arrows
# macro XK_Left "scroll l .1 w"
# macro XK_Up "scroll u .1 w"
# macro XK_Right "scroll r .1 w"
# macro XK_Down "scroll d .1 w"

# Pan 100 percent of the window size with arrows
# macro Shift_XK_Left "scroll l 1 w"
# macro Shift_XK_Up "scroll u 1 w"
# macro Shift_XK_Right "scroll r 1 w"
# macro Shift_XK_Down "scroll d 1 w"

# move 0.05um with arrows
# macro Alt_XK_Left "move l 1l"
# macro Alt_XK_Right "move r 1l"
# macro Alt_XK_Up "move u 1l"
# macro Alt_XK_Down "move d 1l"

# move 1 grid unit with arrows
# macro Alt_Shift_XK_Left "move l 1g"
# macro Alt_Shift_XK_Right "move r 1g"
# macro Alt_Shift_XK_Up "move u 1g"
# macro Alt_Shift_XK_Down "move d 1g"

# stretch 0.05um with arrows
# macro Control_XK_Left "stretch l 1l"
# macro Control_XK_Right "stretch r 1l"
# macro Control_XK_Up "stretch u 1l"
# macro Control_XK_Down "stretch d 1l"

# stretch 1 grid unit with arrows
# macro Control_Shift_XK_Left "stretch l 1g"
# macro Control_Shift_XK_Right "stretch r 1g"
# macro Control_Shift_XK_Up "stretch u 1g"
# macro Control_Shift_XK_Down "stretch d 1g"

# shift mouse wheel bindings for right-left shift
macro Shift_XK_Pointer_Button4 "scroll r .05 w"
macro Shift_XK_Pointer_Button5 "scroll l .05 w"

# control mouse wheel bindings for zoom in/out
macro Control_XK_Pointer_Button4 "zoom 0.70711"
macro Control_XK_Pointer_Button5 "zoom 1.41421"

# Bertrand's original arrow macros
# move 1 grid unit with arrows
macro XK_Left "move l 1g"
macro XK_Right "move r 1g"
macro XK_Up "move u 1g"
macro XK_Down "move d 1g"

# move 0.05um with arrows
macro Control_XK_Left "move l 1l"
macro Control_XK_Right "move r 1l"
macro Control_XK_Up "move u 1l"
macro Control_XK_Down "move d 1l"

# stretch 1 grid unit with arrows
macro Shift_XK_Left "stretch l 1g"
macro Shift_XK_Right "stretch r 1g"
macro Shift_XK_Up "stretch u 1g"
macro Shift_XK_Down "stretch d 1g"

# stretch 0.05um with arrows
macro Control_Shift_XK_Left "stretch l 1l"
macro Control_Shift_XK_Right "stretch r 1l"
macro Control_Shift_XK_Up "stretch u 1l"
macro Control_Shift_XK_Down "stretch d 1l"

# Restore pan function on Alt-key
# Pan 10 percent of the window size with arrows
macro Alt_XK_Left "scroll l .1 w"
macro Alt_XK_Up "scroll u .1 w"
macro Alt_XK_Right "scroll r .1 w"
macro Alt_XK_Down "scroll d .1 w"

# Pan 100 percent of the window size with arrows
macro Alt_Shift_XK_Left "scroll l 1 w"
macro Alt_Shift_XK_Up "scroll u 1 w"
macro Alt_Shift_XK_Right "scroll r 1 w"
macro Alt_Shift_XK_Down "scroll d 1 w"

120
custom/readme.md
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@ -1,11 +1,127 @@
# Custom Cell
# Custom Cell Design

### Prerequisites
#### Prerequisites

* Magic (VERSION TODO) - Layout
* Xschem (VERSION TODO) - Schematic capture
* Netgen-lvs (VERSION TODO) - Layout Vs. Schematic
* Ngspice (VERSION TODO) - SPICE simulation

## 10T RAM Cell

* domino 10T 2R1W
* domino background
* clocked logic family (each gate has a clock)
* clock low, 'precharge' -> node high
* clock high, 'evaluate' -> node based on input(s), can only go low now
* clock signal ensures critical path only traverses through cells during 'evaluate'
* since only switches in one direction, no pmos pullups needed
* effective transistor load is lower for previous stage
* smaller circuit for given capacitance, or
* stronger drive for given capacitance
* faster since no pmos/nmos contention during switching
* noninverting logic
* each domino cell is a single-stage dynamic cell followed by an inverter
* glitchless

<image src="./10T.png">

* array
* in cell, read is bottom of domino (evaluate)
* subarray is 16x12 cells
* 'local eval' is top of domino (precharge) and inverter (NAND2 between (2) subarrays)
* (8) subarrays create 64wx24b 'hard' array
* surrounding logical array does strobe/addr predecode and addr/data latching; (3) subarrays for 64x72_2R1W
* DDR adds double in/out latches, early/late select, and DDR-compatible strobe

## Local Eval

* precharge
* 2:1 select

<image src="./local_eval.png">

* nand2 with precharge pmos pullups on RBL_R, RBL_R
* insert the pullups between p/n

### Precharge Pullup Only

* magic

* load sky130_fd_sc_hd__inv_1 (open technology mgr)
* ```gds``` in console
* now have sky130_fd_sc__hd__inv_1.gds

* klayout sky130_fd_sc__hd__inv_1.gds
* hack
* check with ```magic -dnull -noconsole -rcfile magicdrc_pullup.tcl toysram_local_pullup.gds``` while hacking
* drc clean with nfet side mostly removed; can't remove layer 81 (get drc);
because i haven't removed bottom of cell yet (gnd, etc)?

* now stack these with 12x2 nands to make local_eval_stack


## Tools

```
cd xschem
export PDK_ROOT=/data/projects/open_pdks/sky130
# yikes! nfet references through current dir
ln -s $PDK_ROOT/sky130B/libs.tech/xschem/sky130_fd_pr sky130_fd_pr
xschem --rcfile $PDK_ROOT/sky130B/libs.tech/xschem/xschemrc 10T_toy_xschem.sch

xschem --rcfile $PDK_ROOT/sky130B/libs.tech/xschem/xschemrc local_eval.sch

```

```
cd magic
export PDK_ROOT=/data/projects/open_pdks/sky130
magic -rcfile .magic_tech/.magicrc 10T_toy_magic.mag
console:
'gds' creates gds
'lef writeall' creates lef


magic -rcfile .magic_tech/.magicrc local_eval.mag
# use options->cell mgr to select cell; then can see layout (top is (UNNAMED) at start)
# windows->set editable
# box upper pmos section and 'a' (select all)
# 'move up 50'
```


































### Setup
A template `.magicrc` file can be found in `magic/.magic_tech`. This

45
custom/xschem/local_eval.sch
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@ -0,0 +1,45 @@
v {xschem version=3.1.0 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
N 430 -160 430 -140 {
lab=RBL_R_b}
N 430 -110 480 -110 {
lab=RBL_R_b}
N 430 -190 480 -190 {
lab=GND}
N 430 -140 430 -110 {
lab=RBL_R_b}
N 430 -260 430 -220 {
lab=VDD}
N 400 -140 430 -140 {
lab=RBL_R_b}
N 240 -70 480 -70 {
lab=RBL_L_b}
C {devices/ipin.sym} 390 -190 0 0 {name=p1 lab=PRE_R_b}
C {devices/ipin.sym} 240 -70 0 0 {name=p4 lab=RBL_L_b
}
C {devices/ipin.sym} 400 -140 0 0 {name=p5 lab=RBL_R_b}
C {devices/opin.sym} 600 -90 0 0 {name=p6 lab=RBL_O}
C {sky130_fd_pr/pfet_01v8.sym} 410 -190 0 0 {name=M2
L=0.15
W=0.21
nf=1
mult=1
ad="'int((nf+1)/2) * W/nf * 0.29'"
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
as="'int((nf+2)/2) * W/nf * 0.29'"
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
model=pfet_01v8
spiceprefix=X
}
C {stdcells/NAND2.sym} 540 -90 0 0 {name=x1 VCCPIN=VCC VSSPIN=VSS VCCBPIN=VCC VSSBPIN=VSS}
C {devices/iopin.sym} 430 -260 0 0 {name=p2 lab=VDD
}
C {devices/iopin.sym} 480 -190 0 0 {name=p3 lab=GND
}

96
custom/xschem/local_eval.sch.1
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@ -0,0 +1,96 @@
v {xschem version=3.1.0 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
B 4 200 -370 220 -280 {layer=7}
T {PRE_L} 180 -240 0 0 0.3 0.3 {}
T {PRE_R} 370 -240 0 0 0.3 0.3 {}
N 180 -190 200 -190 {
lab=PRE}
N 240 -160 240 -130 {
lab=RBL_L}
N 240 -260 240 -220 {
lab=VDD}
N 430 -240 430 -220 {
lab=VDD}
N 210 -140 360 -140 {
lab=PRE}
N 360 -140 390 -140 {
lab=PRE}
N 390 -190 390 -140 {
lab=PRE}
N 430 -160 430 -140 {
lab=RBL_R}
N 430 -110 480 -110 {
lab=RBL_R}
N 240 -130 240 -80 {
lab=RBL_L}
N 240 -70 260 -70 {
lab=RBL_L}
N 240 -80 240 -70 {
lab=RBL_L}
N 430 -190 480 -190 {
lab=GND}
N 240 -190 290 -190 {
lab=GND}
N 600 -90 610 -90 {
lab=RBL_Ob}
N 180 -160 240 -160 {
lab=RBL_L}
N 430 -160 520 -160 {
lab=RBL_R}
N 240 -270 240 -260 {
lab=VDD}
N 200 -190 200 -140 {
lab=PRE}
N 200 -140 210 -140 {
lab=PRE}
N 240 -240 430 -240 {
lab=VDD}
N 260 -70 480 -70 {
lab=RBL_L}
N 430 -140 430 -110 {
lab=RBL_R}
C {sky130_fd_pr/pfet_01v8.sym} 220 -190 0 0 {name=M1
L=0.15
W=0.21
nf=1
mult=1
ad="'int((nf+1)/2) * W/nf * 0.29'"
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
as="'int((nf+2)/2) * W/nf * 0.29'"
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
model=pfet_01v8
spiceprefix=X
}
C {devices/lab_pin.sym} 180 -190 0 0 {name=l5 sig_type=std_logic lab=PRE}
C {devices/lab_pin.sym} 240 -270 0 1 {name=l7 sig_type=std_logic lab=VDD}
C {devices/lab_pin.sym} 290 -190 0 1 {name=l11 sig_type=std_logic lab=GND}
C {devices/ipin.sym} 200 -360 0 0 {name=p1 lab=PRE}
C {devices/ipin.sym} 200 -330 0 0 {name=p4 lab=RBL_L}
C {devices/ipin.sym} 200 -310 0 0 {name=p5 lab=RBL_R}
C {devices/opin.sym} 220 -320 0 0 {name=p6 lab=RBL_Ob}
C {sky130_fd_pr/pfet_01v8.sym} 410 -190 0 0 {name=M2
L=0.15
W=0.21
nf=1
mult=1
ad="'int((nf+1)/2) * W/nf * 0.29'"
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
as="'int((nf+2)/2) * W/nf * 0.29'"
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
model=pfet_01v8
spiceprefix=X
}
C {stdcells/NAND2.sym} 540 -90 0 0 {name=x3 VCCPIN=VCC VSSPIN=VSS VCCBPIN=VCC VSSBPIN=VSS}
C {devices/lab_pin.sym} 610 -90 0 1 {name=l1 sig_type=std_logic lab=RBL_Ob}
C {devices/lab_pin.sym} 180 -160 0 0 {name=l2 sig_type=std_logic lab=RBL_L}
C {devices/lab_pin.sym} 520 -160 0 1 {name=l3 sig_type=std_logic lab=RBL_R}
C {devices/lab_pin.sym} 480 -190 0 1 {name=l4 sig_type=std_logic lab=GND}

10
custom/xschem/local_eval.v
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@ -0,0 +1,10 @@
module local_eval (
inout VDD,
inout GND,
//input PRE_L_b,
input RBL_L_b,
input PRE_R_b,
input RBL_R_b,
output RBL_O
);
endmodule

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custom/xschem/lsdl_1.sch
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@ -0,0 +1,80 @@
v {xschem version=3.1.0 file_version=1.2
}
G {}
K {}
V {}
S {}
E {}
T {_q_b} 480 -120 0 0 0.4 0.4 {}
N 460 -290 460 -230 {
lab=#net1}
N 460 -170 460 -130 {
lab=#net2}
N 460 -130 580 -130 {
lab=#net2}
N 500 -320 650 -320 {
lab=_q}
N 660 -320 660 -130 {
lab=_q}
N 650 -320 660 -320 {
lab=_q}
N 660 -130 710 -130 {
lab=_q}
C {sky130_fd_pr/pfet_01v8.sym} 80 -200 0 0 {name=PRECHARGE
L=0.15
W=1
nf=1
mult=1
ad="'int((nf+1)/2) * W/nf * 0.29'"
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
as="'int((nf+2)/2) * W/nf * 0.29'"
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
model=pfet_01v8
spiceprefix=X
}
C {sky130_fd_pr/pfet_01v8.sym} 270 -200 0 0 {name=PREDRIVER
L=0.15
W=1
nf=1
mult=1
ad="'int((nf+1)/2) * W/nf * 0.29'"
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
as="'int((nf+2)/2) * W/nf * 0.29'"
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
model=pfet_01v8
spiceprefix=X
}
C {sky130_fd_pr/pfet_01v8.sym} 440 -200 0 0 {name=CUT_FDBK
L=0.15
W=1
nf=1
mult=1
ad="'int((nf+1)/2) * W/nf * 0.29'"
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
as="'int((nf+2)/2) * W/nf * 0.29'"
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
model=pfet_01v8
spiceprefix=X
}
C {sky130_fd_pr/pfet_01v8.sym} 480 -320 0 1 {name=FDBK
L=0.15
W=1
nf=1
mult=1
ad="'int((nf+1)/2) * W/nf * 0.29'"
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
as="'int((nf+2)/2) * W/nf * 0.29'"
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
model=pfet_01v8
spiceprefix=X
}
C {sky130_stdcells/inv_1.sym} 620 -130 0 0 {name=x1 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ }
C {devices/opin.sym} 710 -130 0 0 {name=p1 lab=_q}

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custom/xschem/simulation/local_eval.net
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@ -0,0 +1,14 @@
** sch_path: /home/wtf/projects/toy-sram/custom/xschem/local_eval.sch
**.subckt local_eval PRE_R_b RBL_L_b RBL_R_b RBL_O VDD GND
*.ipin PRE_R_b
*.ipin RBL_L_b
*.ipin RBL_R_b
*.opin RBL_O
*.iopin VDD
*.iopin GND
XM2 RBL_R_b PRE_R_b VDD GND sky130_fd_pr__pfet_01v8 L=0.15 W=0.21 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
x1 RBL_O RBL_R_b RBL_L_b VCC VSS VCC VSS NAND2
**.ends
.end

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custom/xschem/simulation/local_eval.spice
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@ -0,0 +1,14 @@
** sch_path: /home/wtf/projects/toy-sram/custom/xschem/local_eval.sch
**.subckt local_eval PRE_R_b RBL_L_b RBL_R_b RBL_O VDD GND
*.ipin PRE_R_b
*.ipin RBL_L_b
*.ipin RBL_R_b
*.opin RBL_O
*.iopin VDD
*.iopin GND
XM2 RBL_R_b PRE_R_b VDD GND sky130_fd_pr__pfet_01v8 L=0.15 W=0.21 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
x1 RBL_O RBL_R_b RBL_L_b VCC VSS VCC VSS NAND2
**.ends
.end

1
custom/xschem/sky130_fd_pr
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@ -0,0 +1 @@
/data/projects/open_pdks/sky130/sky130B/libs.tech/xschem/sky130_fd_pr

73
rtl/src/array/regfile_64x24_2r1w.v
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@ -22,7 +22,10 @@

`timescale 1 ps / 1 ps

module regfile_64x24_2r1w (
// 0: gen 8x 16x12 plus local eval 1: gen 4x 32x24 and no local eval
module regfile_64x24_2r1w #(
parameter integer RA_32x24 = 1
) (

input rd0_c_na0,
input rd0_c_a0,
@ -122,6 +125,24 @@ module regfile_64x24_2r1w (
wire [0:11] wbl_48_63_00_11;
wire [0:11] wbl_48_63_12_23;

// 32x24
wire [0:11] rbl0_00_31_00_11;
wire [0:11] rbl0_00_31_12_23;
wire [0:11] rbl1_00_31_00_11;
wire [0:11] rbl1_00_31_12_23;
wire [0:11] wbl_00_31_00_11;
wire [0:11] wbl_00_31_12_23;

wire [0:11] rbl0_32_63_00_11;
wire [0:11] rbl0_32_63_12_23;
wire [0:11] rbl1_32_63_00_11;
wire [0:11] rbl1_32_63_12_23;
wire [0:11] wbl_32_63_00_11;
wire [0:11] wbl_32_63_12_23;

generate

if (RA_32x24 == 0) begin
// subarray cells; 4x2 16w/12b subarrays

// words 00:15
@ -204,6 +225,56 @@ toysram_16x12 r111 (
.WBLb(~wbl_48_63_12_23)
);

end else begin

// subarray cells; 2x2 32w/24b subarrays w/local eval inside between pairs

// words 00:31
toysram_32x12 r00 (
.RWL0({rwl0_00_15_00_11,rwl0_16_31_00_11}),
.RWL1({rwl1_00_15_00_11,rwl1_16_31_00_11}),
.WWL({wwl_00_15_00_11,wwl_16_31_00_11}),
.RBL0(rbl0_00_31_00_11),
.RBL1(rbl1_00_31_00_11),
.WBL(wbl_00_31_00_11),
.WBLb(~wbl_00_31_00_11)
);

toysram_32x12 r01 (
.RWL0({rwl0_00_15_12_23,rwl0_16_31_12_23}),
.RWL1({rwl1_00_15_12_23,rwl1_16_31_12_23}),
.WWL({wwl_00_15_12_23,wwl_16_31_12_23}),
.RBL0(rbl0_00_31_12_23),
.RBL1(rbl1_00_31_12_23),
.WBL(wbl_00_31_12_23),
.WBLb(~wbl_00_31_12_23)
);

// words 32:47
toysram_32x12 r10 (
.RWL0({rwl0_32_47_00_11,rwl0_48_31_00_11}),
.RWL1({rwl1_32_47_00_11,rwl1_48_31_00_11}),
.WWL({wwl_32_47_00_11,wwl_48_31_00_11}),
.RBL0(rbl0_32_63_00_11),
.RBL1(rbl1_32_63_00_11),
.WBL(wbl_32_63_00_11),
.WBLb(~wbl_32_63_00_11)
);

// words 48:63
toysram_32x12 r11 (
.RWL0({rwl0_32_47_12_23,rwl0_48_63_12_23}),
.RWL1({rwl1_32_47_12_23,rwl1_48_63_12_23}),
.WWL({wwl_32_47_12_23,wwl_48_63_12_23}),
.RBL0(rbl0_32_63_12_23),
.RBL1(rbl1_32_63_12_23),
.WBL(wbl_32_63_12_23),
.WBLb(~wbl_32_63_12_23)
);

end
endgenerate

// word lines

assign rwl0_00_15_00_11[0] = rd0_c_na0 & rd0_na1_na2 & rd0_na3 & rd0_na4_na5;

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rtl/src/array/toysram_32x12.v
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@ -0,0 +1,236 @@
// © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.

// Behavioral for 16x12 toysram subarray

`timescale 1 ps / 1 ps

module toysram_32x12 (

input [0:31] RWL0,
input [0:31] RWL1,
input [0:31] WWL,
output [0:11] RBL0,
output [0:11] RBL1,
input [0:11] WBL,
input [0:11] WBLb

);

reg [0:11] mem_00;
reg [0:11] mem_01;
reg [0:11] mem_02;
reg [0:11] mem_03;
reg [0:11] mem_04;
reg [0:11] mem_05;
reg [0:11] mem_06;
reg [0:11] mem_07;
reg [0:11] mem_08;
reg [0:11] mem_09;
reg [0:11] mem_10;
reg [0:11] mem_11;
reg [0:11] mem_12;
reg [0:11] mem_13;
reg [0:11] mem_14;
reg [0:11] mem_15;
reg [0:11] mem_16;
reg [0:11] mem_17;
reg [0:11] mem_18;
reg [0:11] mem_19;
reg [0:11] mem_20;
reg [0:11] mem_21;
reg [0:11] mem_22;
reg [0:11] mem_23;
reg [0:11] mem_24;
reg [0:11] mem_25;
reg [0:11] mem_26;
reg [0:11] mem_27;
reg [0:11] mem_28;
reg [0:11] mem_29;
reg [0:11] mem_30;
reg [0:11] mem_31;

// word-select
// the bits are negative-active at this point in the 16x12 but
// the local eval is done between subarray pairs, so bits are positive going out
assign RBL0 = ~((mem_00 & {12{RWL0[0]}}) & (mem_16 & {12{RWL0[16]}})) &
~((mem_01 & {12{RWL0[1]}}) & (mem_17 & {12{RWL0[17]}})) &
~((mem_02 & {12{RWL0[2]}}) & (mem_18 & {12{RWL0[18]}})) &
~((mem_03 & {12{RWL0[3]}}) & (mem_19 & {12{RWL0[19]}})) &
~((mem_04 & {12{RWL0[4]}}) & (mem_20 & {12{RWL0[20]}})) &
~((mem_05 & {12{RWL0[5]}}) & (mem_21 & {12{RWL0[21]}})) &
~((mem_06 & {12{RWL0[6]}}) & (mem_22 & {12{RWL0[22]}})) &
~((mem_07 & {12{RWL0[7]}}) & (mem_23 & {12{RWL0[23]}})) &
~((mem_08 & {12{RWL0[8]}}) & (mem_24 & {12{RWL0[24]}})) &
~((mem_09 & {12{RWL0[9]}}) & (mem_25 & {12{RWL0[25]}})) &
~((mem_10 & {12{RWL0[10]}}) & (mem_26 & {12{RWL0[26]}})) &
~((mem_11 & {12{RWL0[11]}}) & (mem_27 & {12{RWL0[27]}})) &
~((mem_12 & {12{RWL0[12]}}) & (mem_28 & {12{RWL0[28]}})) &
~((mem_13 & {12{RWL0[13]}}) & (mem_29 & {12{RWL0[29]}})) &
~((mem_14 & {12{RWL0[14]}}) & (mem_30 & {12{RWL0[30]}})) &
~((mem_15 & {12{RWL0[15]}}) & (mem_31 & {12{RWL0[31]}}));

assign RBL0 = ~((mem_00 & {12{RWL1[0]}}) & (mem_16 & {12{RWL1[16]}})) &
~((mem_01 & {12{RWL1[1]}}) & (mem_17 & {12{RWL1[17]}})) &
~((mem_02 & {12{RWL1[2]}}) & (mem_18 & {12{RWL1[18]}})) &
~((mem_03 & {12{RWL1[3]}}) & (mem_19 & {12{RWL1[19]}})) &
~((mem_04 & {12{RWL1[4]}}) & (mem_20 & {12{RWL1[20]}})) &
~((mem_05 & {12{RWL1[5]}}) & (mem_21 & {12{RWL1[21]}})) &
~((mem_06 & {12{RWL1[6]}}) & (mem_22 & {12{RWL1[22]}})) &
~((mem_07 & {12{RWL1[7]}}) & (mem_23 & {12{RWL1[23]}})) &
~((mem_08 & {12{RWL1[8]}}) & (mem_24 & {12{RWL1[24]}})) &
~((mem_09 & {12{RWL1[9]}}) & (mem_25 & {12{RWL1[25]}})) &
~((mem_10 & {12{RWL1[10]}}) & (mem_26 & {12{RWL1[26]}})) &
~((mem_11 & {12{RWL1[11]}}) & (mem_27 & {12{RWL1[27]}})) &
~((mem_12 & {12{RWL1[12]}}) & (mem_28 & {12{RWL1[28]}})) &
~((mem_13 & {12{RWL1[13]}}) & (mem_29 & {12{RWL1[29]}})) &
~((mem_14 & {12{RWL1[14]}}) & (mem_30 & {12{RWL1[30]}})) &
~((mem_15 & {12{RWL1[15]}}) & (mem_31 & {12{RWL1[31]}}));

always @(posedge WWL[0]) begin
mem_00 <= ~WBLb;
end

always @(posedge WWL[1]) begin
mem_01 <= ~WBLb;
end

always @(posedge WWL[2]) begin
mem_02 <= ~WBLb;
end

always @(posedge WWL[3]) begin
mem_03 <= ~WBLb;
end

always @(posedge WWL[4]) begin
mem_04 <= ~WBLb;
end

always @(posedge WWL[5]) begin
mem_05 <= ~WBLb;
end

always @(posedge WWL[6]) begin
mem_06 <= ~WBLb;
end

always @(posedge WWL[7]) begin
mem_07 <= ~WBLb;
end

always @(posedge WWL[8]) begin
mem_08 <= ~WBLb;
end

always @(posedge WWL[9]) begin
mem_09 <= ~WBLb;
end

always @(posedge WWL[10]) begin
mem_10 <= ~WBLb;
end

always @(posedge WWL[11]) begin
mem_11 <= ~WBLb;
end

always @(posedge WWL[12]) begin
mem_12 <= ~WBLb;
end

always @(posedge WWL[13]) begin
mem_13 <= ~WBLb;
end

always @(posedge WWL[14]) begin
mem_14 <= ~WBLb;
end

always @(posedge WWL[15]) begin
mem_15 <= ~WBLb;
end

always @(posedge WWL[16]) begin
mem_16 <= ~WBLb;
end

always @(posedge WWL[17]) begin
mem_17 <= ~WBLb;
end

always @(posedge WWL[18]) begin
mem_18 <= ~WBLb;
end

always @(posedge WWL[19]) begin
mem_19 <= ~WBLb;
end

always @(posedge WWL[20]) begin
mem_20 <= ~WBLb;
end

always @(posedge WWL[21]) begin
mem_21 <= ~WBLb;
end

always @(posedge WWL[22]) begin
mem_22 <= ~WBLb;
end

always @(posedge WWL[23]) begin
mem_23 <= ~WBLb;
end

always @(posedge WWL[24]) begin
mem_24 <= ~WBLb;
end

always @(posedge WWL[25]) begin
mem_25 <= ~WBLb;
end

always @(posedge WWL[26]) begin
mem_26 <= ~WBLb;
end

always @(posedge WWL[27]) begin
mem_27 <= ~WBLb;
end

always @(posedge WWL[28]) begin
mem_28 <= ~WBLb;
end

always @(posedge WWL[29]) begin
mem_29 <= ~WBLb;
end

always @(posedge WWL[30]) begin
mem_30 <= ~WBLb;
end

always @(posedge WWL[31]) begin
mem_31 <= ~WBLb;
end

// assert errors (multiwrite, etc.)

endmodule

83
rtl/src/site-mpw7/cfg.v
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// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.

`timescale 1 ns / 1 ns

`include "../toysram.vh"

// configuration macro
// Manages config registers and routes cmd valids to CFG, CTRL, RAx.

module cfg (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif

input clk,
input rst,
input wb_cmd_val,
input [31:0] wb_cmd_adr,
input wb_cmd_we,
input [3:0] wb_cmd_sel,
input [31:0] wb_cmd_dat,
output wb_rd_ack,
output [31:0] wb_rd_dat,

output [31:0] cmd_adr,
output cmd_we,
output [3:0] cmd_sel,
output [31:0] cmd_dat,

output ctl_cmd_val,
output ra0_cmd_val,
input ctl_rd_ack,
input [31:0] ctl_rd_dat

);

reg ack_q;
wire ack_d;

// FF
always @(posedge clk) begin
if (rst) begin
ack_q <= 1'b0;
end else begin
ack_q <= ack_d;
end
end

// Common
assign cmd_adr = wb_cmd_adr;
assign cmd_we = wb_cmd_we;
assign cmd_sel = wb_cmd_sel;
assign cmd_dat = wb_cmd_dat;

// Macro Routing
// account for ack pipeline back to wb
assign ack_d = ctl_rd_ack;

assign ctl_cmd_val = wb_cmd_val & ~ack_q & ((wb_cmd_adr & `UNIT_MASK) == `CTL_ADDR);
assign ra0_cmd_val = wb_cmd_val & ~ack_q & ((wb_cmd_adr & `UNIT_MASK) == `RA0_ADDR);

assign wb_rd_ack = ctl_rd_ack;
assign wb_rd_dat = ctl_rd_dat;

endmodule

440
rtl/src/site-mpw7/control.v
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// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.

`timescale 1 ns / 1 ns

`include "../toysram.vh"

// control macro
// does stuff

module control (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
input clk,
input rst,

input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,

input ctl_cmd_val,
input ra0_cmd_val,
input [31:0] cmd_adr,
input cmd_we,
input [3:0] cmd_sel,
input [31:0] cmd_dat,
output rd_ack,
output [31:0] rd_dat,

output ra0_clk,
output ra0_rst,
output ra0_cfg_wr,
input [31:0] ra0_cfg_rdat,
output [31:0] ra0_cfg_wdat,
output [31:0] ra0_bist_ctl,
input [31:0] ra0_bist_status,
output ra0_r0_enb,
output [4:0] ra0_r0_adr,
input [31:0] ra0_r0_dat,
output ra0_r1_enb,
output [4:0] ra0_r1_adr,
input [31:0] ra0_r1_dat,
output ra0_w0_enb,
output [4:0] ra0_w0_adr,
output [31:0] ra0_w0_dat

);

reg [31:0] cfg0_q;
wire [31:0] cfg0_d;
reg [4:0] seq_q;
wire [4:0] seq_d;
reg [2:0] rd_wait_q;
wire [2:0] rd_wait_d;
reg [127:0] scan_reg_q;
wire [127:0] scan_reg_d;

wire adr_cfg0;
wire [31:0] cfg0_wrdata;
wire adr_bist;
wire adr_config;
wire special;
wire [1:0] wr_type;
wire ra0_bist_rd;
wire rd_start;
wire [1:0] rd_type;
wire [2:0] rdata_sel;
wire rd_data;

wire test_enable;
wire scan_clk;
wire scan_di;
wire scan_do;
wire [16:0] scan_config;
wire io_ra0_clk;
wire io_ra0_rst;
wire io_ra0_r0_enb;
wire io_ra0_r1_enb;
wire io_ra0_w0_enb;
wire [4:0] io_ra0_r0_adr;
wire [4:0] io_ra0_r1_adr;
wire [4:0] io_ra0_w0_adr;
wire [31:0] io_ra0_w0_dat;

// FF
always @(posedge clk) begin
if (rst) begin
seq_q <= 'hFF;
cfg0_q <= `CFG0_INIT;
rd_wait_q <= 0;
end else begin
seq_q <= seq_d;
cfg0_q <= cfg0_d;
rd_wait_q <= rd_wait_d;
end
end

always @(posedge scan_clk) begin
begin
if (test_enable == 'b1) begin
scan_reg_q <= {scan_reg_q[126:0], scan_di};
end
end
end

always @(posedge io_ra0_clk) begin
if (test_enable == 'b1) begin
scan_reg_q[122:91] <= {ra0_r0_dat};
scan_reg_q[85:54] <= {ra0_r1_dat};
end
end

// GPIO
//
// Scan Controls
// test enable
// scan_clk
// scan_di
// scan_do
//
// Scan Config
// * have a way to single-step on-chip clk so can use it plus scan?
//
// Array Controls
// ra_clk
// ra_rst
// ra_r0_enb
// ra_r1_enb
// ra_w0_enb
//
// Scannable RA0 Reg
// ra0_r0_adr
// ra0_r0_dat
// ra0_r1_adr
// ra0_r1_dat
// ra0_w0_adr
// ra0_w0_dat
//
// Array Read/Write
// 1. scan in adr/dat reg
// 2. activate ra_clk and ra_xx_enb for port control (n cycles)
// 3. scan out adr/dat reg
//
// Scan Logic
// * have control bit(s) to load logic config, array config, bist, whatever from scan_reg
// after it's loaded
// * there are 17 unused bits left in scan_reg also

// ins
assign test_enable = io_in[`PIN_TE];
assign scan_clk = io_in[`PIN_SCAN_CLK];
assign scan_di = io_in[`PIN_SCAN_IN];

assign io_ra0_clk = io_in[`PIN_RA0_CLK];
assign io_ra0_rst = io_in[`PIN_RA0_RST];
assign io_ra0_r0_enb = io_in[`PIN_RA0_R0_EN];
assign io_ra0_r1_enb = io_in[`PIN_RA0_R1_EN];
assign io_ra0_w0_enb = io_in[`PIN_RA0_W0_EN];

// outs
assign io_out[`PIN_SCAN_OUT] = scan_do;
assign io_out[`PIN_RUNMODE] = cfg0_q[31];
assign io_out[`PIN_ERROR] = cfg0_q[30];
assign io_out[`PIN_USER_1] = cfg0_q[29];
assign io_out[`PIN_USER_0] = cfg0_q[28];
assign io_oeb = `PINS_OEB; //wtf do you need to do this anymore? or core does it???

assign io_ra0_r0_adr = scan_reg_q[127:123];
//assign io_ra0_r0_dat = scan_reg_q[122:91]; // loaded by io_ra0_clk
assign io_ra0_r1_adr = scan_reg_q[90:86];
//assign io_ra0_r1_dat = scan_reg_q[85:54]; // loaded by io_ra0_clk
assign io_ra0_w0_adr = scan_reg_q[53:49];
assign io_ra0_w0_dat = scan_reg_q[48:17];

assign scan_config = scan_reg_q[16:0];
assign scan_do = scan_reg_q[127];

// Internal Routing

// CFG0
// 31 Run Mode
// 30 Error
// 29:28 User Outputs [1:0]
// 27:03 Reserved
// 02:00 Read Data Wait Cycles (after cmd cycle)

assign wr_type = cmd_adr[3:2];
assign adr_cfg0 = ctl_cmd_val & ((cmd_adr & `CFG_MASK) == `CFG0_OFFSET);
assign cfg0_wrdata = wr_type == 2'b00 ? cmd_dat :
wr_type == 2'b01 ? cmd_dat | cfg0_q :
wr_type == 2'b10 ? ~cmd_dat & cfg0_q :
cmd_dat ^ cfg0_q;
assign cfg0_d = cmd_we & adr_cfg0 ? cfg0_wrdata : cfg0_q;

// Array Routing

assign adr_bist = ra0_cmd_val & ((cmd_adr & `CFG_MASK) == `BIST_OFFSET);
assign adr_config = ra0_cmd_val & ((cmd_adr & `CFG_MASK) == `CFG_OFFSET);
assign special = adr_bist | adr_config;

assign ra0_bist_ctl = cmd_we & adr_bist ? cmd_dat : 'h00000000;
assign ra0_bist_rd = adr_bist & ~cmd_we;
assign ra0_cfg_wr = cmd_we & adr_config;
assign ra0_cfg_wdat = cmd_dat;

// reads can use r0, r1, or both; if both, return either both hi or both lo data
//wtf probs should be a way to do all r+w
// need a data reg for reads or writes or both
// 1. write data/addr reg, then do a rdtype + extra bit to indicate write from special
// 2. do write + wrtype (00:no read, 01:r0, 10:r1, 11:r01), latch rd port data; if do this, use them for all
// reads, which then enables R0/R1 read to see all bits by reading the data regs; but this requires
// r0,r1,w0 all on addr bus concurrently (type(2), r0(5), r1(5), w0(5) for 32 entries)
// mpw7 supports slave space of 24 bits; some are the local address routing (2-3) but depends on number of arrays

assign rd_type = cmd_adr[15:14]; // port addr 14 bits

// or send test_enable and test_clk/rst to array
assign ra0_clk = test_enable ? io_ra0_clk : clk;
assign ra0_rst = test_enable ? io_ra0_rst : rst;

assign ra0_r0_enb = test_enable ? io_ra0_r0_enb : ra0_cmd_val & ~special & ~cmd_we & (rd_type[1] | ~rd_type[0]);
assign ra0_r1_enb = test_enable ? io_ra0_r1_enb : ra0_cmd_val & ~special & ~cmd_we & (rd_type[1] | rd_type[0]);
assign ra0_r0_adr = test_enable ? io_ra0_r0_adr : cmd_adr[6:2]; // adr=row
// don't confuse programmers and change fields...
//assign ra0_r1_adr = test_enable ? io_ra0_r1_adr : rd_type == 'b01 ? cmd_adr[6:2] : cmd_adr[13:8]; // adr=row
assign ra0_r1_adr = test_enable ? io_ra0_r1_adr : cmd_adr[13:8]; // adr=row
assign ra0_w0_enb = test_enable ? io_ra0_w0_enb : ra0_cmd_val & cmd_we & |cmd_sel; // sel=port
assign ra0_w0_adr = test_enable ? io_ra0_w0_adr : cmd_adr[6:2]; // adr=row
assign ra0_w0_dat = test_enable ? io_ra0_w0_dat : cmd_dat; //

// Command Sequencer
// rd_data in 1+ cycs; all reads use same timing
// writes are ack'd by wb_slave immediately

//tbl cmdseq
//n seq_q seq_d
//n | ctl_cmd_val | rd_start
//n | |ra0_cmd_val | | rd_ack
//n | ||cmd_we | | | rdata_sel
//n | ||| rd_type | | | |
//n | ||| | adr_bist | | | |
//n | ||| | |adr_config | | | |
//n | ||| | || rd_data | | | |
//n | ||| | || | | | | |
//n | ||| | || | | | | |
//n | ||| | || | | | | |
//b 43210 ||| 10 || | 43210 | | 210
//t iiiii iii ii ii i ooooo o o ooo
//*------------------------------------------------
//* Idle ******************************************
//s 11111 00- -- -- - 11111 0 0 000 * ...zzz..zzzzz....
//s 11111 1-1 -- -- - 11111 0 0 000 * write ctl
//s 11111 -11 -- -- - 11111 0 0 000 * write ra
//s 11111 1-0 -- 00 - 00001 1 0 000 * rd ctl cfg
//s 11111 1-0 -- 1- - 00010 1 0 000 * rd bist
//s 11111 1-0 -- -1 - 00011 1 0 000 * rd cfg
//s 11111 -10 00 -- - 00100 1 0 000 * rd r0
//s 11111 -10 01 -- - 00101 1 0 000 * rd r1
//s 11111 -10 10 -- - 00110 1 0 000 * rd r0+r1 lo
//s 11111 -10 11 -- - 00111 1 0 000 * rd r0_r1 hi
//* Read CTL **************************************
//s 00001 --- -- -- 0 00001 0 0 100
//s 00001 --- -- -- 1 11111 0 1 100
//* Read BIST *************************************
//s 00010 --- -- -- 0 00010 0 0 101
//s 00010 --- -- -- 1 11111 0 1 101
//* Read CFG **************************************
//s 00011 --- -- -- 0 00011 0 0 110
//s 00011 --- -- -- 1 11111 0 1 110
//* Read R0 ***************************************
//s 00100 --- -- -- 0 00100 0 0 000
//s 00100 --- -- -- 1 11111 0 1 000
//* Read R1 ***************************************
//s 00101 --- -- -- 0 00101 0 0 001
//s 00101 --- -- -- 1 11111 0 1 001
//* Read R0+R1 Lo *********************************
//s 00110 --- -- -- 0 00110 0 0 010
//s 00110 --- -- -- 1 11111 0 1 010
//* Read R0+R1 Hi *********************************
//s 00111 --- -- -- 0 00111 0 0 011
//s 00111 --- -- -- 1 11111 0 1 011

//*------------------------------------------------
//tbl cmdseq_d

// use same timing for ra accesses and others
assign rd_wait_d = rd_start ? cfg0_q[2:0] :
(rd_wait_q != 0) ? rd_wait_q - 1 :
rd_wait_q;

assign rd_data = rd_wait_q == 0;

assign rd_dat = rdata_sel == 'b000 ? ra0_r0_dat :
rdata_sel == 'b001 ? ra0_r1_dat :
rdata_sel == 'b010 ? {ra0_r1_dat[15:0],ra0_r0_dat[15:0]} :
rdata_sel == 'b011 ? {ra0_r1_dat[31:16],ra0_r0_dat[31:16]} :
rdata_sel == 'b100 ? cfg0_q :
rdata_sel == 'b101 ? ra0_bist_status :
rdata_sel == 'b110 ? ra0_cfg_rdat :
'hFFFFFFFF;

// Generated...
//vtable cmdseq
assign seq_d[4] =
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~ctl_cmd_val & ~ra0_cmd_val) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & cmd_we) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & cmd_we) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
assign seq_d[3] =
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~ctl_cmd_val & ~ra0_cmd_val) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & cmd_we) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & cmd_we) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
assign seq_d[2] =
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~ctl_cmd_val & ~ra0_cmd_val) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & cmd_we) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & cmd_we) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & ~rd_type[1] & ~rd_type[0]) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & ~rd_type[1] & rd_type[0]) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & ~rd_type[0]) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & rd_type[0]) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
assign seq_d[1] =
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~ctl_cmd_val & ~ra0_cmd_val) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & cmd_we) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & cmd_we) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & adr_bist) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & adr_config) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & ~rd_type[0]) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & rd_type[0]) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
assign seq_d[0] =
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~ctl_cmd_val & ~ra0_cmd_val) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & cmd_we) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & cmd_we) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & ~adr_bist & ~adr_config) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & adr_config) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & ~rd_type[1] & rd_type[0]) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & rd_type[0]) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
assign rd_start =
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & ~adr_bist & ~adr_config) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & adr_bist) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & adr_config) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & ~rd_type[1] & ~rd_type[0]) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & ~rd_type[1] & rd_type[0]) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & ~rd_type[0]) |
(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & rd_type[0]);
assign rd_ack =
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
assign rdata_sel[2] =
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
assign rdata_sel[1] =
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
assign rdata_sel[0] =
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) |
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
//vtable cmdseq

endmodule

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rtl/src/site-mpw7/io_intf.v
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// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.

`timescale 1 ns / 1 ns

`include "../toysram.vh"

// I/O interface macro

module io_intf #(
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif

input clk,
input reset
);


endmodule

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rtl/src/site-mpw7/misc.v
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// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.

`timescale 1 ns / 1 ns

`include "../toysram.vh"

// miscellaneous logic macro

module misc #(
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif

input clk,
input reset,

// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oen,

// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7.
inout [`MPRJ_IO_PADS-8:0] analog_io,

// Independent clock (on independent integer divider)
input user_clock2
);

endmodule

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rtl/src/site-mpw7/toysram_site.v
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// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0

`default_nettype none

`include "toysram.vh"

/*
* toysram_site
* user_project for custom toysram cell/array


*-------------------------------------------------------------
*
* user_proj_example
*
* This is an example of a (trivially simple) user project,
* showing how the user project can connect to the logic
* analyzer, the wishbone bus, and the I/O pads.
*
* This project generates an integer count, which is output
* on the user area GPIO pads (digital output only). The
* wishbone connection allows the project to be controlled
* (start and stop) from the management SoC program.
*
* See the testbenches in directory "mprj_counter" for the
* example programs that drive this user project. The three
* testbenches are "io_ports", "la_test1", and "la_test2".
*
*-------------------------------------------------------------
*/

module toysram_site #(
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif

// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,

// Logic Analyzer Signals
`ifndef RA_SIM
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
`endif

// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,

// IRQ
output [2:0] irq
);

wire clk;
wire rst;

wire [31:0] rdata;
wire [31:0] wdata;
wire [31:0] count;

wire valid;
wire [3:0] wstrb;
wire [31:0] la_write;

wire wb_cmd_val;
wire [31:0] wb_cmd_adr;
wire wb_cmd_we;
wire [3:0] wb_cmd_sel;
wire [31:0] wb_cmd_dat;
wire wb_rd_ack;
wire [31:0] wb_rd_dat;
wire [31:0] cmd_adr;
wire cmd_we;
wire [3:0] cmd_sel;
wire [31:0] cmd_dat;
wire ctl_cmd_val;
wire ra0_cmd_val;
wire ctl_rd_ack;
wire [31:0] ctl_rd_dat;
wire ra0_clk;
wire ra0_rst;
wire ra0_cfg_wr;
wire [31:0] ra0_cfg_rdat;
wire [31:0] ra0_cfg_wdat;
wire [31:0] ra0_bist_ctl;
wire [31:0] ra0_bist_status;
wire ra0_r0_enb;
wire [4:0] ra0_r0_adr;
wire [31:0] ra0_r0_dat;
wire ra0_r1_enb;
wire [4:0] ra0_r1_adr;
wire [31:0] ra0_r1_dat;
wire ra0_w0_enb;
wire [4:0] ra0_w0_adr;
wire [31:0] ra0_w0_dat;

// WB MI A
assign valid = wbs_cyc_i && wbs_stb_i;
assign wstrb = wbs_sel_i & {4{wbs_we_i}};
assign wbs_dat_o = rdata;
assign wdata = wbs_dat_i;

// IRQ
assign irq = 3'b000; // Unused


//wtf connect these to the array sigs?
// LA
//assign la_data_out = {{(127-BITS){1'b0}}, count};
assign la_data_out = 0;
// Assuming LA probes [63:32] are for controlling the count register
//assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
assign la_write = 0;

// Assuming LA probes [65:64] are for controlling the count clk & reset
//assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
//assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
assign clk = wb_clk_i;
assign rst = wb_rst_i;

// WB slave
// convert rd/wr commands to/from WB and route to:
// 1. config space
// 2. array space
wb_slave #(
) wb (

`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.clk(clk),
.rst(rst),
.wbs_stb_i(wbs_stb_i),
.wbs_cyc_i(wbs_cyc_i),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_dat_i(wbs_dat_i),
.wbs_adr_i(wbs_adr_i),
.wbs_ack_o(wbs_ack_o),
.wbs_dat_o(wbs_dat_o),
.cmd_val(wb_cmd_val),
.cmd_adr(wb_cmd_adr),
.cmd_we(wb_cmd_we),
.cmd_sel(wb_cmd_sel),
.cmd_dat(wb_cmd_dat),
.rd_ack(wb_rd_ack),
.rd_dat(wb_rd_dat)
);

cfg #(
) cfg (

`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.clk(clk),
.rst(rst),
.wb_cmd_val(wb_cmd_val),
.wb_cmd_adr(wb_cmd_adr),
.wb_cmd_we(wb_cmd_we),
.wb_cmd_sel(wb_cmd_sel),
.wb_cmd_dat(wb_cmd_dat),
.wb_rd_ack(wb_rd_ack),
.wb_rd_dat(wb_rd_dat),
.cmd_adr(cmd_adr),
.cmd_we(cmd_we),
.cmd_sel(cmd_sel),
.cmd_dat(cmd_dat),
.ctl_cmd_val(ctl_cmd_val),
.ra0_cmd_val(ra0_cmd_val),
.ctl_rd_ack(ctl_rd_ack),
.ctl_rd_dat(ctl_rd_dat)
);

/*
// I/O interface
io_intf io (

`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.clk(clk),
.rst(rst)

);
*/

// array and i/o interfaces
control #(
) ctl (
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.clk(clk),
.rst(rst),
.io_in(io_in),
.io_out(io_out),
.io_oeb(io_oeb),
.ctl_cmd_val(ctl_cmd_val),
.ra0_cmd_val(ra0_cmd_val),
.cmd_we(cmd_we),
.cmd_adr(cmd_adr),
.cmd_sel(cmd_sel),
.cmd_dat(cmd_dat),
.rd_ack(ctl_rd_ack),
.rd_dat(ctl_rd_dat),
.ra0_clk(ra0_clk),
.ra0_rst(ra0_rst),
.ra0_cfg_wr(ra0_cfg_wr),
.ra0_cfg_rdat(), //'hFFFFFFFF'), //wtf need to add to ra for read
.ra0_cfg_wdat(ra0_cfg_wdat),
.ra0_bist_ctl(ra0_bist_ctl),
.ra0_bist_status(ra0_bist_status),
.ra0_r0_enb(ra0_r0_enb),
.ra0_r0_adr(ra0_r0_adr),
.ra0_r0_dat(ra0_r0_dat),
.ra0_r1_enb(ra0_r1_enb),
.ra0_r1_adr(ra0_r1_adr),
.ra0_r1_dat(ra0_r1_dat),
.ra0_w0_enb(ra0_w0_enb),
.ra0_w0_adr(ra0_w0_adr),
.ra0_w0_dat(ra0_w0_dat)
);

// arrays
test_ra_sdr_32x32 #(
.RA_SELECT(`RA_SELECT)
) ra_0 (
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.clk(ra0_clk),
.reset(ra0_rst),
.cfg_wr(ra0_cfg_wr),
.cfg_dat(ra0_cfg_wdat),
.bist_ctl(ra0_bist_ctl),
.bist_status(ra0_bist_status),
.rd_enb_0(ra0_r0_enb),
.rd_adr_0(ra0_r0_adr),
.rd_dat_0(ra0_r0_dat),
.rd_enb_1(ra0_r1_enb),
.rd_adr_1(ra0_r1_adr),
.rd_dat_1(ra0_r1_dat),
.wr_enb_0(ra0_w0_enb),
.wr_adr_0(ra0_w0_adr),
.wr_dat_0(ra0_w0_dat)
);

endmodule

`default_nettype wire

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rtl/src/site-mpw7/wb_slave.v
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// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.

`timescale 1 ns / 1 ns

`include "../toysram.vh"

// Wishbone slave macro
// Bridges internal read/write commands to/from Wishbone.
// Only accepts requests matching BASE_ADDR, BASE_MASK; address passed
// on as command does not include upper 4 bits.

module wb_slave #(
parameter BASE_ADDR = 'h30000000,
parameter BASE_MASK = 'hF0000000
) (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
input clk,
input rst,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
output cmd_val,
output [31:0] cmd_adr,
output cmd_we,
output [3:0] cmd_sel,
output [31:0] cmd_dat,
input rd_ack,
input [31:0] rd_dat

);

reg cmd_val_q;
wire cmd_val_d;
reg [31:0] cmd_adr_q;
wire [31:0] cmd_adr_d;
reg cmd_we_q;
wire cmd_we_d;
reg [3:0] cmd_sel_q;
wire [3:0] cmd_sel_d;
reg [31:0] cmd_dat_q;
wire [31:0] cmd_dat_d;
reg rd_ack_q;
wire rd_ack_d;
reg [31:0] rd_dat_q;
wire [31:0] rd_dat_d;

wire stall;
wire base_match;
wire ack;

// FF
always @(posedge clk) begin
if (rst) begin
cmd_val_q <= 1'b0;
cmd_adr_q <= 31'h0;
cmd_we_q <= 1'b0;
cmd_sel_q <= 4'b0;
cmd_dat_q <= 32'h0;
rd_ack_q <= 1'b0;
rd_dat_q <= 32'h0;
end else begin
cmd_val_q <= cmd_val_d;
cmd_adr_q <= cmd_adr_d;
cmd_we_q <= cmd_we_d;
cmd_sel_q <= cmd_sel_d;
cmd_dat_q <= cmd_dat_d;
rd_ack_q <= rd_ack_d;
rd_dat_q <= rd_dat_d;
end
end

// WB

assign stall = 'b0;
assign base_match = wbs_cyc_i & ((wbs_adr_i & BASE_MASK) == BASE_ADDR);

//assign cmd_val_d = (base_match & wbs_stb_i & ~stall) |
// (cmd_val_q & ~ack);
// equiv for wb
assign cmd_val_d = base_match & wbs_stb_i & ~stall & ~ack;
assign cmd_adr_d = {4'b0, wbs_adr_i[27:0]};
assign cmd_we_d = wbs_we_i;
assign cmd_sel_d = wbs_sel_i;
assign cmd_dat_d = wbs_dat_i;
assign ack = rd_ack_q | (cmd_val_q & cmd_we_q); // block with reset?
assign wbs_ack_o = ack;
assign wbs_dat_o = rd_dat_q;

// Outputs

assign cmd_val = cmd_val_q;
assign cmd_adr = cmd_adr_q;
assign cmd_we = cmd_we_q;
assign cmd_sel = cmd_sel_q;
assign cmd_dat = cmd_dat_q;

// Inputs
assign rd_ack_d = rd_ack;
assign rd_dat_d = rd_dat;

endmodule

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rtl/src/site/toysram.vh
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