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add lcb strobe and cleanup array logic

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master
openpowerwtf 2 years ago
parent f46f717930
commit d5fc9bcd00
46 changed files with 988 additions and 2272 deletions
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custom/klayout/local_eval.gds
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doc/IEEE Xplore Full-Text PDF_doublepumprf.pdf
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70
readme.md
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@ -74,3 +74,73 @@ Specific bandwidth can be expressed with two metrics:
## Links

* skywater-pdk.slack.com#toysram


## To Do

### memory cell

* schem, layout, spice, liberty files
* *WRONG!* needs RWL0+RWL1

### 64x24 array

* subarray
* 16x12 gds/lef needed
* lib also?

* eval cell
* can pfet be instantiated in rtl?
* if not, just create a custom cell just for it (le_pullup); can make
different strength versions and connect in rtl
* custom cell; nand2 + pfet pullup gated by precharge for L/R

* quarter
* single macro with L/R subarrays and eval stack between
* then need just decode gap and i/o gap between four quarters

* full with placed std cell decoders, etc.
* single macro with placed netlist cells

### 64x72 array

* rtl for in/out latching

* rtl for strobe (sdr, ddr delay taps)

* rtl for bist?

* rtl for cfg (strobe)

### Verif

* cycle sim for basic 64x72 rtl

* cycle sim for site

* spice sim for 16x12 + eval + 16x12 (quarter)?

### Site

* ring oscillator?

* multiarray?

* scan interface

* wb interface?

### Extras

* auto-convert memory cell and eval to 180 and build site

* lsdl latch in 64x24 for data outs










2
rtl/sim/coco/Makefile_64x72
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@ -20,7 +20,7 @@ SIM ?= icarus

VERILOG_ROOT = src/array

COMPILE_ARGS = -I$(VERILOG_ROOT) -y$(VERILOG_ROOT)
COMPILE_ARGS = -I$(VERILOG_ROOT) -y$(VERILOG_ROOT) -DGENMODE=0

# other options


13
rtl/sim/coco/Makefile_64x72_shard
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@ -18,14 +18,23 @@ SIM ?= icarus

# icarus
#
VERILOG_COMMON = src/array
VERILOG_ROOT = src/array_shard
COMPILE_ARGS = -I$(VERILOG_ROOT) -y$(VERILOG_ROOT)

# CFGINIT
# only no delay works as-is in cycle sim
# 00000000 : disable delay
# 00000001 : enable delay, sdr
# 00000003 : enable delay, ddr
#
#COMPILE_ARGS = -y$(VERILOG_ROOT) -y$(VERILOG_COMMON) -DGENMODE=1 -DCFGINIT=1
COMPILE_ARGS = -y$(VERILOG_ROOT) -y$(VERILOG_COMMON) -DGENMODE=1

# other options

# rtl
TOPLEVEL_LANG = verilog
VERILOG_SOURCES = ./tb_ra_64x72_2r1w.v $(VERILOG_ROOT)/wordlines_comp.v $(VERILOG_ROOT)/sky130_hd.v $(VERILOG_ROOT)/sky130_fd.v
VERILOG_SOURCES = ./tb_ra_64x72_2r1w.v $(VERILOG_ROOT)/sky130_hd.v
TOPLEVEL = tb_ra_64x72_2r1w

# python test

30
rtl/sim/coco/ra_shard_64x72_2r1w.gtkw
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@ -1,16 +1,17 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Tue Nov 8 22:49:44 2022
[*] Tue Nov 15 19:51:18 2022
[*]
[dumpfile] "/data/projects/toy-sram/rtl/sim/coco/tb_ra_64x72.fst"
[dumpfile_mtime] "Tue Nov 8 22:25:44 2022"
[dumpfile_size] 98436
[dumpfile_mtime] "Tue Nov 15 19:33:55 2022"
[dumpfile_size] 99807
[savefile] "/data/projects/toy-sram/rtl/sim/coco/ra_shard_64x72_2r1w.gtkw"
[timestart] 75590
[timestart] 0
[size] 1699 1047
[pos] 188 268
*-12.000000 90500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] 188 267
*-12.000000 1020 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ra_64x72_2r1w.
[treeopen] tb_ra_64x72_2r1w.lcb.
[treeopen] tb_ra_64x72_2r1w.ra.
[treeopen] tb_ra_64x72_2r1w.ra.ra0.
[treeopen] tb_ra_64x72_2r1w.ra.ra0.r000.
@ -35,6 +36,22 @@ tb_ra_64x72_2r1w.wr_enb_0
tb_ra_64x72_2r1w.wr_adr_0[0:5]
tb_ra_64x72_2r1w.wr_dat_0[0:71]
@200
-CNFIG
@22
tb_ra_64x72_2r1w.cnfig.cfg_q[0:31]
tb_ra_64x72_2r1w.cnfig.cfg[0:31]
@200
-LCB
@22
tb_ra_64x72_2r1w.lcb.tap1_sel_q[0:3]
@23
tb_ra_64x72_2r1w.lcb.tap1[0:3]
@28
tb_ra_64x72_2r1w.lcb.tap1_b
tb_ra_64x72_2r1w.lcb.pulse1_b
tb_ra_64x72_2r1w.lcb.pulse2_b
tb_ra_64x72_2r1w.lcb.strobe
@200
-RA
@28
tb_ra_64x72_2r1w.ra.rd_enb_0_q
@ -75,7 +92,6 @@ tb_ra_64x72_2r1w.ra.ra0.r000.WBLb[0:11]
@22
tb_ra_64x72_2r1w.ra.ra0.eval_0x0.RBL1_L[0:11]
tb_ra_64x72_2r1w.ra.ra0.eval_0x0.RBL1_R[0:11]
@23
tb_ra_64x72_2r1w.ra.ra0.eval_0x0.RBL1_O_b[0:11]
[pattern_trace] 1
[pattern_trace] 0

6
rtl/sim/coco/results.xml
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@ -1,6 +1,8 @@
<testsuites name="results">
<testsuite name="all" package="all">
<property name="random_seed" value="8675309" />
<testcase name="tb" classname="tb_ra_64x72" file="/data/projects/toy-sram/rtl/sim/coco/tb_ra_64x72.py" lineno="291" time="83.82325267791748" sim_time_ns="50089.001" ratio_time="597.5549671457156" />
<property name="random_seed" value="1668540834" />
<testcase name="tb" classname="tb_ra_64x72" file="/data/projects/toy-sram/rtl/sim/coco/tb_ra_64x72.py" lineno="293" time="0.2973616123199463" sim_time_ns="107.001" ratio_time="359.8346106789072">
<failure />
</testcase>
</testsuite>
</testsuites>

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rtl/sim/coco/tb_ra_64x72.fst
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4
rtl/sim/coco/tb_ra_64x72.py
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@ -183,6 +183,8 @@ def printstate_32(sim):
async def init(dut, sim):
"""Initialize inputs. """

dut.cfg_wr = 0

return

async def initSite(dut, sim):
@ -297,7 +299,7 @@ async def tb(dut):
sim.ddr = False
sim.clk1xPeriod = 1
sim.clk2x = False
sim.maxCycles = 50000
sim.maxCycles = 10000

# init stuff
await init(dut, sim)

8
rtl/sim/coco/tb_ra_64x72_2r1w.v
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@ -64,7 +64,7 @@ initial begin
#1;
end

ra_lcb_sdr lcb (
ra_lcb #(.GENMODE(`GENMODE)) lcb ( // defined in Makefile

.clk (clk),
.reset (reset),
@ -73,7 +73,7 @@ ra_lcb_sdr lcb (

);

ra_cfg_sdr #(.INIT(-1)) cnfig (
ra_cfg #(.INIT(`CFGINIT)) cnfig ( // null, or defined in Makefile

.clk (clk),
.reset (reset),
@ -83,7 +83,7 @@ ra_cfg_sdr #(.INIT(-1)) cnfig (

);

ra_bist_sdr bist (
ra_bist bist (

.clk (clk),
.reset (reset),
@ -108,7 +108,7 @@ ra_bist_sdr bist (

);

ra_64x72_2r1w ra (
ra_64x72_2r1w #(.GENMODE(0)) ra (

.clk (clk),
.reset (reset),

17
rtl/src/array/address_clock_sdr_2r1w_64.v → rtl/src/array/address_clock.v
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@ -25,7 +25,7 @@

`timescale 1 ns / 1 ns

module address_clock_sdr_2r1w_64 (
module address_clock (

strobe,

@ -100,15 +100,12 @@ module address_clock_sdr_2r1w_64 (
// read address 0
output rd0_c_na0;
output rd0_c_a0;

output rd0_na1_na2;
output rd0_na1_a2;
output rd0_a1_na2;
output rd0_a1_a2;

output rd0_na3;
output rd0_a3;

output rd0_na4_na5;
output rd0_na4_a5;
output rd0_a4_na5;
@ -117,15 +114,12 @@ module address_clock_sdr_2r1w_64 (
// read address 1
output rd1_c_na0;
output rd1_c_a0;

output rd1_na1_na2;
output rd1_na1_a2;
output rd1_a1_na2;
output rd1_a1_a2;

output rd1_na3;
output rd1_a3;

output rd1_na4_na5;
output rd1_na4_a5;
output rd1_a4_na5;
@ -134,15 +128,12 @@ module address_clock_sdr_2r1w_64 (
// write address 0
output wr0_c_na0;
output wr0_c_a0;

output wr0_na1_na2;
output wr0_na1_a2;
output wr0_a1_na2;
output wr0_a1_a2;

output wr0_na3;
output wr0_a3;

output wr0_na4_na5;
output wr0_na4_a5;
output wr0_a4_na5;
@ -150,7 +141,7 @@ module address_clock_sdr_2r1w_64 (

// one predecoder per port

predecode_sdr_64 predecode_r0(
predecode predecode_r0(
.strobe(strobe),
.enable(rd_enb_0),
.address(rd_adr_0),
@ -168,7 +159,7 @@ module address_clock_sdr_2r1w_64 (
.a4_a5(rd0_a4_a5)
);

predecode_sdr_64 predecode_r1(
predecode predecode_r1(
.strobe(strobe),
.enable(rd_enb_1),
.address(rd_adr_1),
@ -186,7 +177,7 @@ module address_clock_sdr_2r1w_64 (
.a4_a5(rd1_a4_a5)
);

predecode_sdr_64 predecode_w0(
predecode predecode_w0(
.strobe(strobe),
.enable(wr_enb_0),
.address(wr_adr_0),

2
rtl/src/array/predecode_sdr_64.v → rtl/src/array/predecode.v
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@ -21,7 +21,7 @@

`timescale 1 ns / 1 ns

module predecode_sdr_64(
module predecode (

strobe,
enable,

16
rtl/src/array/ra_64x72_2r1w.v
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@ -23,12 +23,13 @@

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_64x72_2r1w #(
parameter GENMODE = `GENMODE, // 0=NoDelay, 1=Delay

parameter GENMODE, // 0=NoDelay, 1=Delay
parameter LATCHRD = 1 // 1=latch read data, 0=unlatched

) (

input clk,
input reset,
input strobe,
@ -142,17 +143,10 @@ endgenerate

// toysram_16x12 component needs rising edge to check wwl
assign strobe_int = strobe;
/*
// don't use the clock as data in sim mode
if (`GENMODE == 0)
assign strobe_int = 1'b1;
else
assign strobe_int = strobe;
*/

// generate the controls for the array

address_clock_sdr_2r1w_64 #(
address_clock #(

.GENMODE(GENMODE)


6
rtl/src/array_shard/ra_bist_sdr.v → rtl/src/array/ra_bist.v
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@ -34,9 +34,7 @@

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_bist_sdr (
module ra_bist (

clk,
reset,
@ -61,7 +59,7 @@ module ra_bist_sdr (

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay
parameter GENMODE = 0; // 0=NoDelay, 1=Delay

input clk;
input reset;

169
rtl/src/array/ra_bist_ddr.v
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@ -1,169 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Local BIST for arrays
// Pass array inputs through, or generate locally for test/manual access.
// May want status_valid, ctl_valid sigs.
// Want separate cmds for enter/exit functional?
// ctl:
// 00000000 - functional mode
// 800000aa - read adr aa
// 900000aa - write adr aa (next 3 cycs are data)
// F00000tt - run bist test tt
//
// status:
//
//

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_bist_ddr (

clk,
reset,
ctl,
status,
rd0_enb_in,
rd0_adr_in,
rd1_enb_in,
rd1_adr_in,
rd2_enb_in,
rd2_adr_in,
rd3_enb_in,
rd3_adr_in,
wr0_enb_in,
wr0_adr_in,
wr0_dat_in,
wr1_enb_in,
wr1_adr_in,
wr1_dat_in,
rd0_enb_out,
rd0_adr_out,
rd0_dat,
rd1_enb_out,
rd1_adr_out,
rd1_dat,
rd2_enb_out,
rd2_adr_out,
rd2_dat,
rd3_enb_out,
rd3_adr_out,
rd3_dat,
wr0_enb_out,
wr0_adr_out,
wr0_dat_out,
wr1_enb_out,
wr1_adr_out,
wr1_dat_out

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay

input clk;
input reset;
input [0:31] ctl;

input rd0_enb_in;
input [0:5] rd0_adr_in;
input rd1_enb_in;
input [0:5] rd1_adr_in;
input rd2_enb_in;
input [0:5] rd2_adr_in;
input rd3_enb_in;
input [0:5] rd3_adr_in;
input wr0_enb_in;
input [0:5] wr0_adr_in;
input [0:71] wr0_dat_in;
input wr1_enb_in;
input [0:5] wr1_adr_in;
input [0:71] wr1_dat_in;

output [0:31] status;
output rd0_enb_out;
output [0:5] rd0_adr_out;
input [0:71] rd0_dat;
output rd1_enb_out;
output [0:5] rd1_adr_out;
input [0:71] rd1_dat;
output rd2_enb_out;
output [0:5] rd2_adr_out;
input [0:71] rd2_dat;
output rd3_enb_out;
output [0:5] rd3_adr_out;
input [0:71] rd3_dat;
output wr0_enb_out;
output [0:5] wr0_adr_out;
output [0:71] wr0_dat_out;
output wr1_enb_out;
output [0:5] wr1_adr_out;
output [0:71] wr1_dat_out;

reg [0:5] seq_q;
wire [0:5] seq_d;
wire active;
wire bist_rd0_enb;
wire [0:5] bist_rd0_adr;
wire bist_rd1_enb;
wire [0:5] bist_rd1_adr;
wire bist_rd2_enb;
wire [0:5] bist_rd2_adr;
wire bist_rd3_enb;
wire [0:5] bist_rd3_adr;
wire bist_wr0_enb;
wire [0:5] bist_wr0_adr;
wire [0:71] bist_wr0_dat;
wire bist_wr1_enb;
wire [0:5] bist_wr1_adr;
wire [0:71] bist_wr1_dat;

// ff
always @ (posedge clk) begin
if (reset)
seq_q <= 6'h3F;
else
seq_q <= seq_d;
end

// do something
assign seq_d = seq_q;
assign active = seq_q != 6'h3F;
assign status = 0;

// outputs
assign rd0_enb_out = (active) ? bist_rd0_enb : rd0_enb_in;
assign rd0_adr_out = (active) ? bist_rd0_adr : rd0_adr_in;
assign rd1_enb_out = (active) ? bist_rd1_enb : rd1_enb_in;
assign rd1_adr_out = (active) ? bist_rd1_adr : rd1_adr_in;
assign rd2_enb_out = (active) ? bist_rd2_enb : rd2_enb_in;
assign rd2_adr_out = (active) ? bist_rd2_adr : rd2_adr_in;
assign rd3_enb_out = (active) ? bist_rd3_enb : rd3_enb_in;
assign rd3_adr_out = (active) ? bist_rd3_adr : rd3_adr_in;
assign wr0_enb_out = (active) ? bist_wr0_enb : wr0_enb_in;
assign wr0_adr_out = (active) ? bist_wr0_adr : wr0_adr_in;
assign wr0_dat_out = (active) ? bist_wr0_dat : wr0_dat_in;
assign wr1_enb_out = (active) ? bist_wr1_enb : wr1_enb_in;
assign wr1_adr_out = (active) ? bist_wr1_adr : wr1_adr_in;
assign wr1_dat_out = (active) ? bist_wr1_dat : wr1_dat_in;

endmodule

123
rtl/src/array/ra_bist_sdr.v
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@ -1,123 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Local BIST for arrays
// Pass array inputs through, or generate locally for test/manual access.
// May want status_valid, ctl_valid sigs.
// Want separate cmds for enter/exit functional?
// ctl:
// 00000000 - functional mode
// 800000aa - read adr aa
// 900000aa - write adr aa (next 3 cycs are data)
// F00000tt - run bist test tt
//
// status:
//
//

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_bist_sdr (

clk,
reset,
ctl,
status,
rd0_enb_in,
rd0_adr_in,
rd1_enb_in,
rd1_adr_in,
wr0_enb_in,
wr0_adr_in,
wr0_dat_in,
rd0_enb_out,
rd0_adr_out,
rd0_dat,
rd1_enb_out,
rd1_adr_out,
rd1_dat,
wr0_enb_out,
wr0_adr_out,
wr0_dat_out

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay

input clk;
input reset;
input [31:0] ctl;

input rd0_enb_in;
input [5:0] rd0_adr_in;
input rd1_enb_in;
input [5:0] rd1_adr_in;
input wr0_enb_in;
input [5:0] wr0_adr_in;
input [71:0] wr0_dat_in;

output [31:0] status;
output rd0_enb_out;
output [5:0] rd0_adr_out;
input [71:0] rd0_dat;
output rd1_enb_out;
output [5:0] rd1_adr_out;
input [71:0] rd1_dat;
output wr0_enb_out;
output [5:0] wr0_adr_out;
output [71:0] wr0_dat_out;

reg [5:0] seq_q;
wire [5:0] seq_d;
wire active;
wire bist_rd0_enb;
wire [5:0] bist_rd0_adr;
wire bist_rd1_enb;
wire [5:0] bist_rd1_adr;
wire bist_wr0_enb;
wire [5:0] bist_wr0_adr;
wire [71:0] bist_wr0_dat;

// ff
always @ (posedge clk) begin
if (reset)
seq_q <= 6'h3F;
else
seq_q <= seq_d;
end

// do something
assign seq_d = seq_q;
assign active = seq_q != 6'h3F;
assign status = 0;

// outputs
assign rd0_enb_out = (active) ? bist_rd0_enb : rd0_enb_in;
assign rd0_adr_out = (active) ? bist_rd0_adr : rd0_adr_in;
assign rd1_enb_out = (active) ? bist_rd1_enb : rd1_enb_in;
assign rd1_adr_out = (active) ? bist_rd1_adr : rd1_adr_in;
assign wr0_enb_out = (active) ? bist_wr0_enb : wr0_enb_in;
assign wr0_adr_out = (active) ? bist_wr0_adr : wr0_adr_in;
assign wr0_dat_out = (active) ? bist_wr0_dat : wr0_dat_in;
//assign rd0_dat = (active) ? haven't done anything here yet

endmodule

29
rtl/src/array/ra_cfg_sdr.v → rtl/src/array/ra_cfg.v
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@ -23,29 +23,22 @@

`timescale 1 ns / 1 ns

`include "toysram.vh"
module ra_cfg #(

module ra_cfg_sdr(
parameter GENMODE = 0, // 0=NoDelay, 1=Delay
parameter INIT = 0

clk,
reset,
cfg_wr,
cfg_dat,
cfg
) (
input clk,
input reset,
input cfg_wr,
input [0:31] cfg_dat,
output [0:31] cfg

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay
parameter INIT = `LCBSDR_CONFIGWIDTH'b0;

input clk;
input reset;
input cfg_wr;
input [0:`LCBSDR_CONFIGWIDTH-1] cfg_dat;
output [0:`LCBSDR_CONFIGWIDTH-1] cfg;

reg [0:`LCBSDR_CONFIGWIDTH-1] cfg_q;
wire [0:`LCBSDR_CONFIGWIDTH-1] cfg_d;
reg [0:31] cfg_q;
wire [0:31] cfg_d;

// ff
always @ (posedge clk) begin

65
rtl/src/array/ra_cfg_ddr.v
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@ -1,65 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Local Configuration for arrays
//

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_cfg_ddr (

clk,
reset,
cfg_wr,
cfg_dat,
cfg

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay
parameter INIT = `LCBDDR_CONFIGWIDTH'b0;

input clk;
input reset;
input cfg_wr;
input [0:`LCBDDR_CONFIGWIDTH-1] cfg_dat;
output [0:`LCBDDR_CONFIGWIDTH-1] cfg;

reg [0:`LCBDDR_CONFIGWIDTH-1] cfg_q;
wire [0:`LCBDDR_CONFIGWIDTH-1] cfg_d;

// ff
always @ (posedge clk) begin
if (reset)
cfg_q <= INIT;
else
cfg_q <= cfg_d;
end

// do something
assign cfg_d = (cfg_wr) ? cfg_dat : cfg_q;

// outputs
assign cfg = cfg_q;

endmodule

51
rtl/src/array/ra_delay.v
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@ -1,51 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Delay Block for Array Strobe

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_delay(

i,
o

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay

input i;
output o;

// generate strobe
generate

if (GENMODE == 0)
assign o = 1;
else begin
assign o = 1'bX; //wtf this will be a specific tech cell instantiation
end

endgenerate

endmodule

166
rtl/src/array/ra_lcb.v
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@ -0,0 +1,166 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Local Clock Buffer for arrays
// Generates sim or implementation logic, depending on GENMODE.

`timescale 1 ns / 1 ns

/*
Config_LCB

31 enable delay
30 sdr=0 ddr=1
28:29 tap1 sel (pulse width)
26:27 tap2 sel (pulse 2 separation gross)
24:25 tap3 sel (pulse 2 separation fine)
*/

module ra_lcb #(

parameter GENMODE = 0

) (
input clk,
input reset,
input [0:31] cfg,
output strobe

);

reg no_delay_q;
reg no_delay_b_q;
reg ddr_q;
reg [0:3] tap1_sel_q;
reg [0:2] tap2_sel_q;
reg [0:3] tap3_sel_q;

wire [0:3] delay1;
wire [0:3] tap1;
wire tap1_b;
wire pulse1_b;
wire delay2_b;
wire [0:15] delay2;
wire [0:2] tap2;
wire tap2_b;
wire [0:3] delay3;
wire [0:3] tap3;
wire pulse2_b;
wire pulse;

// predecode and keep locally
//wtf make these dff cells?
always @(posedge clk) begin

no_delay_q <= ~cfg[31];
no_delay_b_q <= cfg[31];
ddr_q <= cfg[30];
tap1_sel_q[0] <= cfg[28:29] == 2'b00;
tap1_sel_q[1] <= cfg[28:29] == 2'b01;
tap1_sel_q[2] <= cfg[28:29] == 2'b10;
tap1_sel_q[3] <= cfg[28:29] == 2'b11;
tap2_sel_q[0] <= cfg[26:27] == 2'b00;
tap2_sel_q[1] <= cfg[26:27] == 2'b01;
tap2_sel_q[2] <= cfg[26:27] == 2'b10;
//tap2_sel_q[3] <= cfg[26:27] == 2'b11;
tap3_sel_q[0] <= cfg[24:25] == 2'b00;
tap3_sel_q[1] <= cfg[24:25] == 2'b01;
tap3_sel_q[2] <= cfg[24:25] == 2'b10;
tap3_sel_q[3] <= cfg[24:25] == 2'b11;

end

// generate strobe
// array needs strobe to precharge the bitlines before evaluate phase
// strobe is AND'd with enable/addr to create precharge signal -> strobe=0 == precharge
// sdr: one strobe per clk
// ddr: two strobes per clk; early/late select for addr sel/data out latch

generate

if (GENMODE == 0)

assign strobe = ~clk;

else begin

genvar i;

// dly1 - create pulse 1 (and 2 if ddr) width
sky130_fd_sc_hd__buf_1 dly1_0(.A(clk), .X(delay1[0]));

//wtf need to size properly; could spread into 1/2/4/7 etc.
// there are buf_[1,2,4,6,8,12,16]
// bufbuf_[8,16]
// clkbuf_[1,2,4,8,16]
// clkdlybufs15_[1,2]
// clkdlybufs18_[1,2]
// clkdlybufs25_[1,2]
// blkdlybufs50_[1,2]
for (i = 1; i < 4; i = i + 1) begin
sky130_fd_sc_hd__buf_1 dly1_n(.A(delay1[i-1]), .X(delay1[i]));
end

for (i = 0; i < 4; i = i + 1) begin
sky130_fd_sc_hd__and2_1 dly1_sel(.A(tap1_sel_q[i]), .B(delay1[i]), .X(tap1[i]));
end

sky130_fd_sc_hd__nor4_1 dly1_or(.A(tap1[0]), .B(tap1[1]), .C(tap1[2]), .D(tap1[3]), .X(tap1_b));

sky130_fd_sc_hd__nand2_1 dly1_out(.A(clk), .B(tap1_b), .Y(pulse1_b));

// dly2 - create pulse 2 separation (disable for sdr)
sky130_fd_sc_hd__and2_1 dly2_in(.A(ddr_q), .B(pulse1_b), .X(delay2_b));
sky130_fd_sc_hd__inv_1 dly2_0(.A(delay2_b), .Y(delay2[0]));

// 2-stage
// +8/12/16
// +0/1/2/3
for (i = 1; i < 16; i = i + 1) begin
sky130_fd_sc_hd__inv_1 dly2_n(.A(delay2[i-1]), .Y(delay2[i]));
end

sky130_fd_sc_hd__and2_1 dly2_sel0(.A(tap2_sel_q[0]), .B(delay2[7]), .X(tap2[0]));
sky130_fd_sc_hd__and2_1 dly2_sel1(.A(tap2_sel_q[1]), .B(delay2[11]), .X(tap2[1]));
sky130_fd_sc_hd__and2_1 dly2_sel2(.A(tap2_sel_q[2]), .B(delay2[15]), .X(tap2[2]));

sky130_fd_sc_hd__or3_1 dly3_0(.A(tap2[0]), .B(tap2[1]), .C(tap2[2]), .X(delay3[0]));
for (i = 1; i < 4; i = i + 1) begin
sky130_fd_sc_hd__buf_1 dly3_n (.A(delay3[i-1]), .X(delay3[i]));
end

for (i = 0; i < 4; i = i + 1) begin
sky130_fd_sc_hd__and2_1 dly3_sel(.A(tap3_sel_q[i]), .B(delay3[i]), .X(tap3[i]));
end

sky130_fd_sc_hd__nor4_1 dly3_out(.A(tap3[0]), .B(tap3[1]), .C(tap3[2]), .D(tap3[3]), .X(pulse2_b));

// combine
sky130_fd_sc_hd__nand2_1 pulse12(.A(pulse1_b), .B(pulse2_b), .Y(pulse));

// select and invert (neg-active precharge)
sky130_fd_sc_hd__a22oi_1 strobe_out(.A1(no_delay_q), .A2(clk), .B1(no_delay_b_q), .B2(pulse), .X(strobe));

end

endgenerate

endmodule

124
rtl/src/array/ra_lcb_ddr.v
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@ -1,124 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Local Clock Buffer for arrays
// Generates sim or implementation logic, depending on GENMODE.
// el_sel is early/late select (first/second pulse of cycle)

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_lcb_ddr (

clk, // =clk2x for genmode=0
reset, // used for genmode=1? seems not; could kill strobe with it
cfg,
strobe,
el_sel

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay

input clk;
input reset;
input [0:`LCBDDR_CONFIGWIDTH-1] cfg;
output strobe;
output el_sel;

//generate
// if (GENMODE == 0)
reg el_sel_q;
//endgenerate

wire clk_dly;
wire o0;
wire o1;
wire clk_dly2;

// generate strobe
generate

if (GENMODE == 0)
assign strobe = !clk & !reset; // strobe is inverted clk2x
else begin

// generate a strobe for ddr - is late pulse a delay of this, or gen'd independently from clk??
// clk -> [delay] -> * --------------------- * -- and ---
// | -- [delay] --- inv ---|

// first edge delay
ra_delay d0 (
.i(clk),
.o(o0)
);
// remaining
/*
genvar i;
for (i = 1; i < `MAX_PULSE_DELAYS-1; i = i + 1) begin : d1
ra_delay (
.i()
.o()
)
end
*/
// select tap based on cfg

assign clk_dly = o0;

// first width delay
ra_delay w0 (
.i(clk_dly),
.o(o1)
);

// remaining
// select tap based on cfg

assign clk_dly2 = o1;

// create strobe
assign strobe = clk_dly & !clk_dly2;

end

endgenerate

// generate el_sel
generate

if (GENMODE == 0) begin
always @ (posedge clk)
if (reset)
el_sel_q <= 1'b0;
else
el_sel_q <= !el_sel_q;
assign el_sel = el_sel_q;
end else begin

// el_sel is delayed version of clk

end

endgenerate

endmodule

99
rtl/src/array/ra_lcb_sdr.v
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@ -1,99 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Local Clock Buffer for arrays
// Generates sim or implementation logic, depending on GENMODE.

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_lcb_sdr (

clk,
reset,
cfg,
strobe

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay
input clk;
input reset;
input [0:`LCBSDR_CONFIGWIDTH-1] cfg;
output strobe;

wire clk_dly;
wire i;
wire o0;
wire o1;
wire clk_dly2;

// generate strobe
generate

if (GENMODE == 0)
assign strobe = !clk & !reset;
else begin

// generate a strobe for sdr
// clk -> [delay] -> * --------------------- * -- and ---
// | -- [delay] --- inv ---|

// first edge delay
ra_delay d0 (
.i(i),
.o(o0)
);
// remaining
/*
genvar i;
for (i = 1; i < `MAX_PULSE_DELAYS-1; i = i + 1) begin : d1
ra_delay (
.i()
.o()
)
end
*/
// select tap based on cfg

assign clk_dly = o0;

// first width delay
ra_delay w0 (
.i(clk_dly),
.o(o1)
);

// remaining
// select tap based on cfg

assign clk_dly2 = o1;


// create strobe
assign strobe = clk_dly & !clk_dly2;

end

endgenerate

endmodule

16
rtl/src/array/regfile_64x24_2r1w.v
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@ -125,7 +125,7 @@ module regfile_64x24_2r1w (
// subarray cells; 4x2 16w/12b subarrays

// words 00:15
toysram_16x12 w00 (
toysram_16x12 r000 (
.RWL0(rwl0_00_15_00_11),
.RWL1(rwl1_00_15_00_11),
.WWL(wwl_00_15_00_11),
@ -134,7 +134,7 @@ toysram_16x12 w00 (
.WBL(wbl_00_15_00_11),
.WBLb(~wbl_00_15_00_11)
);
toysram_16x12 w01 (
toysram_16x12 r001 (
.RWL0(rwl0_00_15_12_23),
.RWL1(rwl1_00_15_12_23),
.WWL(wwl_00_15_12_23),
@ -145,7 +145,7 @@ toysram_16x12 w01 (
);

// words 16:31
toysram_16x12 w10 (
toysram_16x12 r010 (
.RWL0(rwl0_16_31_00_11),
.RWL1(rwl1_16_31_00_11),
.WWL(wwl_16_31_00_11),
@ -154,7 +154,7 @@ toysram_16x12 w10 (
.WBL(wbl_16_31_00_11),
.WBLb(~wbl_16_31_00_11)
);
toysram_16x12 w11 (
toysram_16x12 r011 (
.RWL0(rwl0_16_31_12_23),
.RWL1(rwl1_16_31_12_23),
.WWL(wwl_16_31_12_23),
@ -165,7 +165,7 @@ toysram_16x12 w11 (
);

// words 32:47
toysram_16x12 w20 (
toysram_16x12 r100 (
.RWL0(rwl0_32_47_00_11),
.RWL1(rwl1_32_47_00_11),
.WWL(wwl_32_47_00_11),
@ -174,7 +174,7 @@ toysram_16x12 w20 (
.WBL(wbl_32_47_00_11),
.WBLb(~wbl_32_47_00_11)
);
toysram_16x12 w21 (
toysram_16x12 r101 (
.RWL0(rwl0_32_47_12_23),
.RWL1(rwl1_32_47_12_23),
.WWL(wwl_32_47_12_23),
@ -185,7 +185,7 @@ toysram_16x12 w21 (
);

// words 48:63
toysram_16x12 w30 (
toysram_16x12 r110 (
.RWL0(rwl0_48_63_00_11),
.RWL1(rwl1_48_63_00_11),
.WWL(wwl_48_63_00_11),
@ -194,7 +194,7 @@ toysram_16x12 w30 (
.WBL(wbl_48_63_00_11),
.WBLb(~wbl_48_63_00_11)
);
toysram_16x12 w31 (
toysram_16x12 r111 (
.RWL0(rwl0_48_63_12_23),
.RWL1(rwl1_48_63_12_23),
.WWL(wwl_48_63_12_23),

8
rtl/src/array/toysram.vh
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@ -1,8 +0,0 @@
// Global Parameters for ToySRAM Testsite

`define GENMODE 0 // 0=NoDelay, 1=Delay

// RA LCB
`define LCBSDR_CONFIGWIDTH 16
`define LCBDDR_CONFIGWIDTH 32

2
rtl/src/array_shard/toysram_16x12_wrapper.v → rtl/src/array/toysram_16x12_wrapper.v
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@ -29,7 +29,7 @@ module toysram_16x12 (
output [0:11] RBL0,
output [0:11] RBL1,
input [0:11] WBL,
input [0:11] WBLb,
input [0:11] WBLb
);

endmodule

207
rtl/src/array_shard/address_clock_sdr_2r1w_64.v
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@ -1,207 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Address and clocking synthesized logic for SDR 2r1w 64 word array
// Two modes:
// 1. nodelay: for sim, FPGA - clk (SDR) or clk2x (DDR) produce strobe
// 2. delay: for implementation, strobes are configured, and derived from clk

`timescale 1 ns / 1 ns

module address_clock_sdr_2r1w_64 (

strobe,

// address ports and associated enable signals
rd_enb_0,
rd_adr_0,
rd_enb_1,
rd_adr_1,
wr_enb_0,
wr_adr_0,

// predecoded address signal
// four groups of one hot encoded signals
// read address 0
rd0_c_na0,
rd0_c_a0,
rd0_na1_na2,
rd0_na1_a2,
rd0_a1_na2,
rd0_a1_a2,
rd0_na3,
rd0_a3,
rd0_na4_na5,
rd0_na4_a5,
rd0_a4_na5,
rd0_a4_a5,

// read address 1
rd1_c_na0,
rd1_c_a0,
rd1_na1_na2,
rd1_na1_a2,
rd1_a1_na2,
rd1_a1_a2,
rd1_na3,
rd1_a3,
rd1_na4_na5,
rd1_na4_a5,
rd1_a4_na5,
rd1_a4_a5,

// write address 0
wr0_c_na0,
wr0_c_a0,
wr0_na1_na2,
wr0_na1_a2,
wr0_a1_na2,
wr0_a1_a2,
wr0_na3,
wr0_a3,
wr0_na4_na5,
wr0_na4_a5,
wr0_a4_na5,
wr0_a4_a5

);

parameter GENMODE = 0; // 0=NoDelay, 1=Delay

input strobe;

// address ports and associated enable signals
input rd_enb_0;
input [0:5] rd_adr_0;
input rd_enb_1;
input [0:5] rd_adr_1;
input wr_enb_0;
input [0:5] wr_adr_0;

// predecoded address signal
// four groups of one hot encoded signals
// read address 0
output rd0_c_na0;
output rd0_c_a0;

output rd0_na1_na2;
output rd0_na1_a2;
output rd0_a1_na2;
output rd0_a1_a2;

output rd0_na3;
output rd0_a3;

output rd0_na4_na5;
output rd0_na4_a5;
output rd0_a4_na5;
output rd0_a4_a5;

// read address 1
output rd1_c_na0;
output rd1_c_a0;

output rd1_na1_na2;
output rd1_na1_a2;
output rd1_a1_na2;
output rd1_a1_a2;

output rd1_na3;
output rd1_a3;

output rd1_na4_na5;
output rd1_na4_a5;
output rd1_a4_na5;
output rd1_a4_a5;

// write address 0
output wr0_c_na0;
output wr0_c_a0;

output wr0_na1_na2;
output wr0_na1_a2;
output wr0_a1_na2;
output wr0_a1_a2;

output wr0_na3;
output wr0_a3;

output wr0_na4_na5;
output wr0_na4_a5;
output wr0_a4_na5;
output wr0_a4_a5;

// one predecoder per port

predecode_sdr_64 predecode_r0(
.strobe(strobe),
.enable(rd_enb_0),
.address(rd_adr_0),
.c_na0(rd0_c_na0),
.c_a0(rd0_c_a0),
.na1_na2(rd0_na1_na2),
.na1_a2(rd0_na1_a2),
.a1_na2(rd0_a1_na2),
.a1_a2(rd0_a1_a2),
.na3(rd0_na3),
.a3(rd0_a3),
.na4_na5(rd0_na4_na5),
.na4_a5(rd0_na4_a5),
.a4_na5(rd0_a4_na5),
.a4_a5(rd0_a4_a5)
);

predecode_sdr_64 predecode_r1(
.strobe(strobe),
.enable(rd_enb_1),
.address(rd_adr_1),
.c_na0(rd1_c_na0),
.c_a0(rd1_c_a0),
.na1_na2(rd1_na1_na2),
.na1_a2(rd1_na1_a2),
.a1_na2(rd1_a1_na2),
.a1_a2(rd1_a1_a2),
.na3(rd1_na3),
.a3(rd1_a3),
.na4_na5(rd1_na4_na5),
.na4_a5(rd1_na4_a5),
.a4_na5(rd1_a4_na5),
.a4_a5(rd1_a4_a5)
);

predecode_sdr_64 predecode_w0(
.strobe(strobe),
.enable(wr_enb_0),
.address(wr_adr_0),
.c_na0(wr0_c_na0),
.c_a0(wr0_c_a0),
.na1_na2(wr0_na1_na2),
.na1_a2(wr0_na1_a2),
.a1_na2(wr0_a1_na2),
.a1_a2(wr0_a1_a2),
.na3(wr0_na3),
.a3(wr0_a3),
.na4_na5(wr0_na4_na5),
.na4_a5(wr0_na4_a5),
.a4_na5(wr0_a4_na5),
.a4_a5(wr0_a4_a5)
);

endmodule

90
rtl/src/array_shard/decode_wordlines_32.v
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@ -0,0 +1,90 @@
// © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions & limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make & use the physical chip.

// Wordline decodes
// Two versions:
// 12-in -> 64 one-hot (all selects, 1 comp used)
// 11-in -> 32 one-hot (half selects, 2 comps used)

`timescale 1 ps / 1 ps

// (c0)(12) -> 8 one-hots A0:A7
// (xa3)(45)-> 4 one-hots B0:B3 (xa3 is na3 for one decoder, a3 for the other)
// A x B -> 32 one-hots W00:W31
module decode_wordlines_32 (

input c_na0,
input c_a0,
input na1_na2,
input na1_a2,
input a1_na2,
input a1_a2,
input xa3,
input na4_na5,
input na4_a5,
input a4_na5,
input a4_a5,
output [0:31] wl

);

wire [0:7] dcd_a_b;
wire [0:7] dcd_a;
wire [0:3] dcd_b_b;
wire [0:3] dcd_b;
wire [0:31] wl_b;

sky130_fd_sc_hd__nand2_2 DCD_A0b (.A(c_na0), .B(na1_na2), .Y(dcd_a_b[0]));
sky130_fd_sc_hd__nand2_2 DCD_A1b (.A(c_na0), .B(na1_a2), .Y(dcd_a_b[1]));
sky130_fd_sc_hd__nand2_2 DCD_A2b (.A(c_na0), .B(a1_na2), .Y(dcd_a_b[2]));
sky130_fd_sc_hd__nand2_2 DCD_A3b (.A(c_na0), .B(a1_a2), .Y(dcd_a_b[3]));
sky130_fd_sc_hd__nand2_2 DCD_A4b (.A(c_a0), .B(na1_na2), .Y(dcd_a_b[4]));
sky130_fd_sc_hd__nand2_2 DCD_A5b (.A(c_a0), .B(na1_a2), .Y(dcd_a_b[5]));
sky130_fd_sc_hd__nand2_2 DCD_A6b (.A(c_a0), .B(a1_na2), .Y(dcd_a_b[6]));
sky130_fd_sc_hd__nand2_2 DCD_A7b (.A(c_a0), .B(a1_a2), .Y(dcd_a_b[7]));

sky130_fd_sc_hd__inv_2 DCD_A0 (.A(dcd_a_b[0]), .Y(dcd_a[0]));
sky130_fd_sc_hd__inv_2 DCD_A1 (.A(dcd_a_b[1]), .Y(dcd_a[1]));
sky130_fd_sc_hd__inv_2 DCD_A2 (.A(dcd_a_b[2]), .Y(dcd_a[2]));
sky130_fd_sc_hd__inv_2 DCD_A3 (.A(dcd_a_b[3]), .Y(dcd_a[3]));
sky130_fd_sc_hd__inv_2 DCD_A4 (.A(dcd_a_b[4]), .Y(dcd_a[4]));
sky130_fd_sc_hd__inv_2 DCD_A5 (.A(dcd_a_b[5]), .Y(dcd_a[5]));
sky130_fd_sc_hd__inv_2 DCD_A6 (.A(dcd_a_b[6]), .Y(dcd_a[6]));
sky130_fd_sc_hd__inv_2 DCD_A7 (.A(dcd_a_b[7]), .Y(dcd_a[7]));

sky130_fd_sc_hd__nand2_2 DCD_B0b (.A(xa3), .B(na4_na5), .Y(dcd_b_b[0]));
sky130_fd_sc_hd__nand2_2 DCD_B1b (.A(xa3), .B(na4_a5), .Y(dcd_b_b[1]));
sky130_fd_sc_hd__nand2_2 DCD_B2b (.A(xa3), .B(a4_na5), .Y(dcd_b_b[2]));
sky130_fd_sc_hd__nand2_2 DCD_B3b (.A(xa3), .B(a4_a5), .Y(dcd_b_b[3]));

sky130_fd_sc_hd__inv_2 DCD_B0 (.A(dcd_b_b[0]), .Y(dcd_b[0]));
sky130_fd_sc_hd__inv_2 DCD_B1 (.A(dcd_b_b[1]), .Y(dcd_b[1]));
sky130_fd_sc_hd__inv_2 DCD_B2 (.A(dcd_b_b[2]), .Y(dcd_b[2]));
sky130_fd_sc_hd__inv_2 DCD_B3 (.A(dcd_b_b[3]), .Y(dcd_b[3]));

genvar i, j;
generate
for (i = 0; i < 8; i = i + 1) begin
for (j = 0; j < 4; j = j + 1) begin
sky130_fd_sc_hd__nand2_2 DCD_Cb (.A(dcd_a[i]), .B(dcd_b[j]), .Y(wl_b[i*4+j]));
sky130_fd_sc_hd__inv_2 DCD_C (.A(wl_b[i*4+j]), .Y(wl[i*4+j]));
end
end
endgenerate
endmodule

100
rtl/src/array_shard/decode_wordlines_64.v
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@ -0,0 +1,100 @@
// © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions & limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make & use the physical chip.

// Wordline decodes
// Two versions:
// 12-in -> 64 one-hot (all selects, 1 comp used)
// 11-in -> 32 one-hot (half selects, 2 comps used)

`timescale 1 ps / 1 ps

// (c0)(12) -> 8 one-hots A0:A7
// (3)(45) -> 8 one-hots B0:B7
// A x B -> 64 one-hots W00:W63
module decode_wordlines_64 (

input c_na0,
input c_a0,
input na1_na2,
input na1_a2,
input a1_na2,
input a1_a2,
input na3,
input a3,
input na4_na5,
input na4_a5,
input a4_na5,
input a4_a5,
output [0:63] wl

);

wire [0:7] dcd_a_b;
wire [0:7] dcd_a;
wire [0:7] dcd_b_b;
wire [0:7] dcd_b;
wire [0:63] wl_b;

sky130_fd_sc_hd__nand2_2 DCD_A0b (.A(c_na0), .B(na1_na2), .Y(dcd_a_b[0]));
sky130_fd_sc_hd__nand2_2 DCD_A1b (.A(c_na0), .B(na1_a2), .Y(dcd_a_b[1]));
sky130_fd_sc_hd__nand2_2 DCD_A2b (.A(c_na0), .B(a1_na2), .Y(dcd_a_b[2]));
sky130_fd_sc_hd__nand2_2 DCD_A3b (.A(c_na0), .B(a1_a2), .Y(dcd_a_b[3]));
sky130_fd_sc_hd__nand2_2 DCD_A4b (.A(c_a0), .B(na1_na2), .Y(dcd_a_b[4]));
sky130_fd_sc_hd__nand2_2 DCD_A5b (.A(c_a0), .B(na1_a2), .Y(dcd_a_b[5]));
sky130_fd_sc_hd__nand2_2 DCD_A6b (.A(c_a0), .B(a1_na2), .Y(dcd_a_b[6]));
sky130_fd_sc_hd__nand2_2 DCD_A7b (.A(c_a0), .B(a1_a2), .Y(dcd_a_b[7]));

sky130_fd_sc_hd__inv_2 DCD_A0 (.A(dcd_a_b[0]), .Y(dcd_a[0]));
sky130_fd_sc_hd__inv_2 DCD_A1 (.A(dcd_a_b[1]), .Y(dcd_a[1]));
sky130_fd_sc_hd__inv_2 DCD_A2 (.A(dcd_a_b[2]), .Y(dcd_a[2]));
sky130_fd_sc_hd__inv_2 DCD_A3 (.A(dcd_a_b[3]), .Y(dcd_a[3]));
sky130_fd_sc_hd__inv_2 DCD_A4 (.A(dcd_a_b[4]), .Y(dcd_a[4]));
sky130_fd_sc_hd__inv_2 DCD_A5 (.A(dcd_a_b[5]), .Y(dcd_a[5]));
sky130_fd_sc_hd__inv_2 DCD_A6 (.A(dcd_a_b[6]), .Y(dcd_a[6]));
sky130_fd_sc_hd__inv_2 DCD_A7 (.A(dcd_a_b[7]), .Y(dcd_a[7]));

sky130_fd_sc_hd__nand2_2 DCD_B0b (.A(na3), .B(na4_na5), .Y(dcd_b_b[0]));
sky130_fd_sc_hd__nand2_2 DCD_B1b (.A(na3), .B(na4_a5), .Y(dcd_b_b[1]));
sky130_fd_sc_hd__nand2_2 DCD_B2b (.A(na3), .B(a4_na5), .Y(dcd_b_b[2]));
sky130_fd_sc_hd__nand2_2 DCD_B3b (.A(na3), .B(a4_a5), .Y(dcd_b_b[3]));
sky130_fd_sc_hd__nand2_2 DCD_B4b (.A(a3), .B(na4_na5), .Y(dcd_b_b[4]));
sky130_fd_sc_hd__nand2_2 DCD_B5b (.A(a3), .B(na4_a5), .Y(dcd_b_b[5]));
sky130_fd_sc_hd__nand2_2 DCD_B6b (.A(a3), .B(a4_na5), .Y(dcd_b_b[6]));
sky130_fd_sc_hd__nand2_2 DCD_B7b (.A(a3), .B(a4_a5), .Y(dcd_b_b[6]));

sky130_fd_sc_hd__inv_2 DCD_B0 (.A(dcd_b_b[0]), .Y(dcd_b[0]));
sky130_fd_sc_hd__inv_2 DCD_B1 (.A(dcd_b_b[1]), .Y(dcd_b[1]));
sky130_fd_sc_hd__inv_2 DCD_B2 (.A(dcd_b_b[2]), .Y(dcd_b[2]));
sky130_fd_sc_hd__inv_2 DCD_B3 (.A(dcd_b_b[3]), .Y(dcd_b[3]));
sky130_fd_sc_hd__inv_2 DCD_B4 (.A(dcd_b_b[4]), .Y(dcd_b[4]));
sky130_fd_sc_hd__inv_2 DCD_B5 (.A(dcd_b_b[5]), .Y(dcd_b[5]));
sky130_fd_sc_hd__inv_2 DCD_B6 (.A(dcd_b_b[6]), .Y(dcd_b[6]));
sky130_fd_sc_hd__inv_2 DCD_B7 (.A(dcd_b_b[7]), .Y(dcd_b[7]));

genvar i, j;
generate
for (i = 0; i < 8; i = i + 1) begin
for (j = 0; j < 8; j = j + 1) begin
sky130_fd_sc_hd__nand2_2 DCD_Cb (.A(dcd_a[i]), .B(dcd_b[j]), .Y(wl_b[i*8+j]));
sky130_fd_sc_hd__inv_2 DCD_C (.A(wl_b[i*8+j]), .Y(wl[i*8+j]));
end
end
endgenerate

endmodule

8
rtl/src/array_shard/local_eval_comp.v
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@ -29,9 +29,11 @@ module local_eval (

);

sky130_fd_pr__pfet_01v8 PRE_L (.G(PRE_b), .D(RBL_L));
sky130_fd_pr__pfet_01v8 PRE_R (.G(PRE_b), .D(RBL_R));
sky130_fd_sc_hd__nand2_1 SEL (.A(RBL_L), .B(RBL_R), .X(RBL_O_b));
//wtf hacked 1/2 inverters
//toysram_local_pullup PRE_L (.PRE_b(PRE_b), .RBL(RBL_L));
//toysram_local_pullup PRE_R (.PRE_b(PRE_b), .RBL(RBL_R));

sky130_fd_sc_hd__nand2_1 SEL (.A(RBL_L), .B(RBL_R), .Y(RBL_O_b));

endmodule


124
rtl/src/array_shard/predecode_sdr_64.v
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@ -1,124 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.

// Predecode of 6 address bits into 4 one hot encodings

`timescale 1 ns / 1 ns

module predecode_sdr_64(

strobe,
enable,
address,
// 12 predecoded address lines 2 - 4 - 2 - 4 one hot encoding
c_na0, // clock and not address(0)
c_a0, // clock and address(0)
na1_na2,// not address(1) and not address(2)
na1_a2, // not address(1) and address(2)
a1_na2, // address(1) and not address(2)
a1_a2, // address(1) and address(2)
na3, // not address(3)
a3, // address(3)
na4_na5,// not address(4) and not address(5)
na4_a5, // not address(4) address(5)
a4_na5, // address(4) and not address(5)
a4_a5 // address(4) and address(5)

);
input strobe;
input enable;
input [0:5] address;
output c_na0;
output c_a0;
output na1_na2;
output na1_a2;
output a1_na2;
output a1_a2; // address(1) and address(2)
output na3; // not address(3)
output a3; // address(3)
output na4_na5;// not address(4) and not address(5)
output na4_a5; // not address(4) address(5)
output a4_na5; // address(4) and not address(5)
output a4_a5; // address(4) and address(5)

wire clock_enable;
wire [0:5] inv_address;
wire n_c_na0;
wire n_c_a0;
wire n_na1_na2;
wire n_na1_a2;
wire n_a1_na2;
wire n_a1_a2;
wire n_na4_na5;
wire n_na4_a5;
wire n_a4_na5;
wire n_a4_a5;

// and read or write enable with clock
// does this need to be SSB placed?
assign clock_enable = strobe & enable;

assign inv_address[0] = (~(address[0]));
assign inv_address[1] = (~(address[1]));
assign inv_address[2] = (~(address[2]));
assign inv_address[3] = (~(address[3]));
assign inv_address[4] = (~(address[4]));
assign inv_address[5] = (~(address[5]));

// A(0) address predecode and gating with clock

assign c_na0 = clock_enable & inv_address[0];
assign c_a0 = clock_enable & address[0];
// A(1:2) address predecode
assign na1_na2 = inv_address[1] & inv_address[2];
assign na1_a2 = inv_address[1] & address[2];
assign a1_na2 = address[1] & inv_address[2];
assign a1_a2 = address[1] & address[2];

// A(3) address predecode

assign na3 = inv_address[3];
assign a3 = address[3];
// A(4:5) address predecode
assign na4_na5 = inv_address[4] & inv_address[5];

assign na4_a5 = inv_address[4] & address[5];
assign a4_na5 = address[4] & inv_address[5];
assign a4_a5 = address[4] & address[5];

endmodule

8
rtl/src/array_shard/ra_64x72_2r1w.v
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@ -23,11 +23,11 @@

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_64x72_2r1w #(
parameter GENMODE = `GENMODE, // 0=NoDelay, 1=Delay

parameter GENMODE, // 0=NoDelay, 1=Delay
parameter LATCHRD = 1 // 1=latch read data, 0=unlatched

) (
input clk,
input reset,
@ -142,7 +142,7 @@ endgenerate

assign strobe_int = strobe;

address_clock_sdr_2r1w_64 #(
address_clock #(

.GENMODE(GENMODE)


169
rtl/src/array_shard/ra_bist_ddr.v
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@ -1,169 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Local BIST for arrays
// Pass array inputs through, or generate locally for test/manual access.
// May want status_valid, ctl_valid sigs.
// Want separate cmds for enter/exit functional?
// ctl:
// 00000000 - functional mode
// 800000aa - read adr aa
// 900000aa - write adr aa (next 3 cycs are data)
// F00000tt - run bist test tt
//
// status:
//
//

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_bist_ddr (

clk,
reset,
ctl,
status,
rd0_enb_in,
rd0_adr_in,
rd1_enb_in,
rd1_adr_in,
rd2_enb_in,
rd2_adr_in,
rd3_enb_in,
rd3_adr_in,
wr0_enb_in,
wr0_adr_in,
wr0_dat_in,
wr1_enb_in,
wr1_adr_in,
wr1_dat_in,
rd0_enb_out,
rd0_adr_out,
rd0_dat,
rd1_enb_out,
rd1_adr_out,
rd1_dat,
rd2_enb_out,
rd2_adr_out,
rd2_dat,
rd3_enb_out,
rd3_adr_out,
rd3_dat,
wr0_enb_out,
wr0_adr_out,
wr0_dat_out,
wr1_enb_out,
wr1_adr_out,
wr1_dat_out

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay

input clk;
input reset;
input [0:31] ctl;

input rd0_enb_in;
input [0:5] rd0_adr_in;
input rd1_enb_in;
input [0:5] rd1_adr_in;
input rd2_enb_in;
input [0:5] rd2_adr_in;
input rd3_enb_in;
input [0:5] rd3_adr_in;
input wr0_enb_in;
input [0:5] wr0_adr_in;
input [0:71] wr0_dat_in;
input wr1_enb_in;
input [0:5] wr1_adr_in;
input [0:71] wr1_dat_in;

output [0:31] status;
output rd0_enb_out;
output [0:5] rd0_adr_out;
input [0:71] rd0_dat;
output rd1_enb_out;
output [0:5] rd1_adr_out;
input [0:71] rd1_dat;
output rd2_enb_out;
output [0:5] rd2_adr_out;
input [0:71] rd2_dat;
output rd3_enb_out;
output [0:5] rd3_adr_out;
input [0:71] rd3_dat;
output wr0_enb_out;
output [0:5] wr0_adr_out;
output [0:71] wr0_dat_out;
output wr1_enb_out;
output [0:5] wr1_adr_out;
output [0:71] wr1_dat_out;

reg [0:5] seq_q;
wire [0:5] seq_d;
wire active;
wire bist_rd0_enb;
wire [0:5] bist_rd0_adr;
wire bist_rd1_enb;
wire [0:5] bist_rd1_adr;
wire bist_rd2_enb;
wire [0:5] bist_rd2_adr;
wire bist_rd3_enb;
wire [0:5] bist_rd3_adr;
wire bist_wr0_enb;
wire [0:5] bist_wr0_adr;
wire [0:71] bist_wr0_dat;
wire bist_wr1_enb;
wire [0:5] bist_wr1_adr;
wire [0:71] bist_wr1_dat;

// ff
always @ (posedge clk) begin
if (reset)
seq_q <= 6'h3F;
else
seq_q <= seq_d;
end

// do something
assign seq_d = seq_q;
assign active = seq_q != 6'h3F;
assign status = 0;

// outputs
assign rd0_enb_out = (active) ? bist_rd0_enb : rd0_enb_in;
assign rd0_adr_out = (active) ? bist_rd0_adr : rd0_adr_in;
assign rd1_enb_out = (active) ? bist_rd1_enb : rd1_enb_in;
assign rd1_adr_out = (active) ? bist_rd1_adr : rd1_adr_in;
assign rd2_enb_out = (active) ? bist_rd2_enb : rd2_enb_in;
assign rd2_adr_out = (active) ? bist_rd2_adr : rd2_adr_in;
assign rd3_enb_out = (active) ? bist_rd3_enb : rd3_enb_in;
assign rd3_adr_out = (active) ? bist_rd3_adr : rd3_adr_in;
assign wr0_enb_out = (active) ? bist_wr0_enb : wr0_enb_in;
assign wr0_adr_out = (active) ? bist_wr0_adr : wr0_adr_in;
assign wr0_dat_out = (active) ? bist_wr0_dat : wr0_dat_in;
assign wr1_enb_out = (active) ? bist_wr1_enb : wr1_enb_in;
assign wr1_adr_out = (active) ? bist_wr1_adr : wr1_adr_in;
assign wr1_dat_out = (active) ? bist_wr1_dat : wr1_dat_in;

endmodule

65
rtl/src/array_shard/ra_cfg_ddr.v
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@ -1,65 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Local Configuration for arrays
//

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_cfg_ddr (

clk,
reset,
cfg_wr,
cfg_dat,
cfg

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay
parameter INIT = `LCBDDR_CONFIGWIDTH'b0;

input clk;
input reset;
input cfg_wr;
input [0:`LCBDDR_CONFIGWIDTH-1] cfg_dat;
output [0:`LCBDDR_CONFIGWIDTH-1] cfg;

reg [0:`LCBDDR_CONFIGWIDTH-1] cfg_q;
wire [0:`LCBDDR_CONFIGWIDTH-1] cfg_d;

// ff
always @ (posedge clk) begin
if (reset)
cfg_q <= INIT;
else
cfg_q <= cfg_d;
end

// do something
assign cfg_d = (cfg_wr) ? cfg_dat : cfg_q;

// outputs
assign cfg = cfg_q;

endmodule

65
rtl/src/array_shard/ra_cfg_sdr.v
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@ -1,65 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Local Configuration for arrays
//

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_cfg_sdr(

clk,
reset,
cfg_wr,
cfg_dat,
cfg

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay
parameter INIT = `LCBSDR_CONFIGWIDTH'b0;

input clk;
input reset;
input cfg_wr;
input [0:`LCBSDR_CONFIGWIDTH-1] cfg_dat;
output [0:`LCBSDR_CONFIGWIDTH-1] cfg;

reg [0:`LCBSDR_CONFIGWIDTH-1] cfg_q;
wire [0:`LCBSDR_CONFIGWIDTH-1] cfg_d;

// ff
always @ (posedge clk) begin
if (reset)
cfg_q <= INIT;
else
cfg_q <= cfg_d;
end

// do something
assign cfg_d = (cfg_wr) ? cfg_dat : cfg_q;

// outputs
assign cfg = cfg_q;

endmodule

51
rtl/src/array_shard/ra_delay.v
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@ -1,51 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Delay Block for Array Strobe

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_delay(

i,
o

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay

input i;
output o;

// generate strobe
generate

if (GENMODE == 0)
assign o = 1;
else begin
assign o = 1'bX; //wtf this will be a specific tech cell instantiation
end

endgenerate

endmodule

124
rtl/src/array_shard/ra_lcb_ddr.v
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@ -1,124 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Local Clock Buffer for arrays
// Generates sim or implementation logic, depending on GENMODE.
// el_sel is early/late select (first/second pulse of cycle)

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_lcb_ddr (

clk, // =clk2x for genmode=0
reset, // used for genmode=1? seems not; could kill strobe with it
cfg,
strobe,
el_sel

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay

input clk;
input reset;
input [0:`LCBDDR_CONFIGWIDTH-1] cfg;
output strobe;
output el_sel;

//generate
// if (GENMODE == 0)
reg el_sel_q;
//endgenerate

wire clk_dly;
wire o0;
wire o1;
wire clk_dly2;

// generate strobe
generate

if (GENMODE == 0)
assign strobe = !clk & !reset; // strobe is inverted clk2x
else begin

// generate a strobe for ddr - is late pulse a delay of this, or gen'd independently from clk??
// clk -> [delay] -> * --------------------- * -- and ---
// | -- [delay] --- inv ---|

// first edge delay
ra_delay d0 (
.i(clk),
.o(o0)
);
// remaining
/*
genvar i;
for (i = 1; i < `MAX_PULSE_DELAYS-1; i = i + 1) begin : d1
ra_delay (
.i()
.o()
)
end
*/
// select tap based on cfg

assign clk_dly = o0;

// first width delay
ra_delay w0 (
.i(clk_dly),
.o(o1)
);

// remaining
// select tap based on cfg

assign clk_dly2 = o1;

// create strobe
assign strobe = clk_dly & !clk_dly2;

end

endgenerate

// generate el_sel
generate

if (GENMODE == 0) begin
always @ (posedge clk)
if (reset)
el_sel_q <= 1'b0;
else
el_sel_q <= !el_sel_q;
assign el_sel = el_sel_q;
end else begin

// el_sel is delayed version of clk

end

endgenerate

endmodule

99
rtl/src/array_shard/ra_lcb_sdr.v
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@ -1,99 +0,0 @@
// © IBM Corp. 2021
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.


// Local Clock Buffer for arrays
// Generates sim or implementation logic, depending on GENMODE.

`timescale 1 ns / 1 ns

`include "toysram.vh"

module ra_lcb_sdr (

clk,
reset,
cfg,
strobe

);

parameter GENMODE = `GENMODE; // 0=NoDelay, 1=Delay
input clk;
input reset;
input [0:`LCBSDR_CONFIGWIDTH-1] cfg;
output strobe;

wire clk_dly;
wire i;
wire o0;
wire o1;
wire clk_dly2;

// generate strobe
generate

if (GENMODE == 0)
assign strobe = !clk & !reset;
else begin

// generate a strobe for sdr
// clk -> [delay] -> * --------------------- * -- and ---
// | -- [delay] --- inv ---|

// first edge delay
ra_delay d0 (
.i(i),
.o(o0)
);
// remaining
/*
genvar i;
for (i = 1; i < `MAX_PULSE_DELAYS-1; i = i + 1) begin : d1
ra_delay (
.i()
.o()
)
end
*/
// select tap based on cfg

assign clk_dly = o0;

// first width delay
ra_delay w0 (
.i(clk_dly),
.o(o1)
);

// remaining
// select tap based on cfg

assign clk_dly2 = o1;


// create strobe
assign strobe = clk_dly & !clk_dly2;

end

endgenerate

endmodule

1
rtl/src/array_shard/regfile_shard_64x24_2r1w_comp.v
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@ -470,6 +470,7 @@ wordlines_comp_32 dcd_1 (

// local eval

//wtf move to decode!
// precharge repower
// during precharge c_na0 = c_a0 = 0
// 4 copies to 000/010, 001/011, 100/110, 101,111 quads

8
rtl/src/array_shard/sky130_fd.v
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@ -1,8 +0,0 @@
`timescale 1 ps / 1 ps

module sky130_fd_pr__pfet_01v8 (
input G,
input D
);

endmodule

130
rtl/src/array_shard/sky130_hd.v
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@ -51,13 +51,13 @@ module sky130_fd_sc_hd__and2_1 (
endmodule

module sky130_fd_sc_hd__nand2 (
X,
Y,
A,
B
);

// Module ports
output X;
output Y;
input A;
input B;

@ -68,17 +68,17 @@ module sky130_fd_sc_hd__nand2 (
supply0 VNB ;

// Name Output Other arguments
nand nand0 (X, A, B);
nand nand0 (Y, A, B);

endmodule

module sky130_fd_sc_hd__nand2_1 (
X,
Y,
A,
B
);

output X;
output Y;
input A;
input B;

@ -89,7 +89,7 @@ module sky130_fd_sc_hd__nand2_1 (
supply0 VNB ;

sky130_fd_sc_hd__nand2 base (
.X(X),
.Y(Y),
.A(A),
.B(B)
);
@ -97,12 +97,12 @@ module sky130_fd_sc_hd__nand2_1 (
endmodule

module sky130_fd_sc_hd__nand2_2 (
X,
Y,
A,
B
);

output X;
output Y;
input A;
input B;

@ -113,7 +113,7 @@ module sky130_fd_sc_hd__nand2_2 (
supply0 VNB ;

sky130_fd_sc_hd__nand2 base (
.X(X),
.Y(Y),
.A(A),
.B(B)
);
@ -190,6 +190,52 @@ module sky130_fd_sc_hd__or2_2 (

endmodule

module sky130_fd_sc_hd__or3_1 (
X,
A,
B,
C
);

output X;
input A;
input B;
input C;

// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;

or or0 (X, A, B, C);

endmodule

module sky130_fd_sc_hd__nor4_1 (
X,
A,
B,
C,
D
);

output X;
input A;
input B;
input C;
input D;

// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;

nor nor0 (X, A, B, C, D);

endmodule

module sky130_fd_sc_hd__xor2 (
X,
A,
@ -537,6 +583,72 @@ module sky130_fd_sc_hd__a22o_1 (

endmodule

module sky130_fd_sc_hd__o22ai_1 (
X ,
A1,
A2,
B1,
B2
);

output X ;
input A1;
input A2;
input B1;
input B2;

// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;

// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;

// Name Output Other arguments
or or0 (or0_out , B1, B2 );
or or1 (or1_out , A1, A2 );
and and0 (and0_out_X, or1_out, or0_out);
not inv0 (X , and0_out_X );

endmodule

module sky130_fd_sc_hd__a22oi_1 (
X ,
A1,
A2,
B1,
B2
);

output X ;
input A1;
input A2;
input B1;
input B2;

// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;

// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;

// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
not inv0 (X , or0_out_X );

endmodule

module sky130_fd_sc_hd__a32o (
X ,
A1,

8
rtl/src/array_shard/toysram.vh
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@ -1,8 +0,0 @@
// Global Parameters for ToySRAM Testsite

`define GENMODE 0 // 0=NoDelay, 1=Delay

// RA LCB
`define LCBSDR_CONFIGWIDTH 16
`define LCBDDR_CONFIGWIDTH 32

156
rtl/src/array_shard/toysram_16x12.v
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@ -1,156 +0,0 @@
// © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions and limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make and use the physical chip.

// Behavioral for 16x12 toysram subarray

`timescale 1 ps / 1 ps

module toysram_16x12 (

input [0:15] RWL0,
input [0:15] RWL1,
input [0:15] WWL,
output [0:11] RBL0,
output [0:11] RBL1,
input [0:11] WBL,
input [0:11] WBLb

);

reg [0:11] mem_00;
reg [0:11] mem_01;
reg [0:11] mem_02;
reg [0:11] mem_03;
reg [0:11] mem_04;
reg [0:11] mem_05;
reg [0:11] mem_06;
reg [0:11] mem_07;
reg [0:11] mem_08;
reg [0:11] mem_09;
reg [0:11] mem_10;
reg [0:11] mem_11;
reg [0:11] mem_12;
reg [0:11] mem_13;
reg [0:11] mem_14;
reg [0:11] mem_15;

// word-select
// the bits are negative-active at this point
// the cell outputs 0 if stored '1' AND RWLx; RBLx[0:11] are dot-AND'ed
assign RBL0 = ~(mem_00 & {12{RWL0[0]}}) &
~(mem_01 & {12{RWL0[1]}}) &
~(mem_02 & {12{RWL0[2]}}) &
~(mem_03 & {12{RWL0[3]}}) &
~(mem_04 & {12{RWL0[4]}}) &
~(mem_05 & {12{RWL0[5]}}) &
~(mem_06 & {12{RWL0[6]}}) &
~(mem_07 & {12{RWL0[7]}}) &
~(mem_08 & {12{RWL0[8]}}) &
~(mem_09 & {12{RWL0[9]}}) &
~(mem_10 & {12{RWL0[10]}}) &
~(mem_11 & {12{RWL0[11]}}) &
~(mem_12 & {12{RWL0[12]}}) &
~(mem_13 & {12{RWL0[13]}}) &
~(mem_14 & {12{RWL0[14]}}) &
~(mem_15 & {12{RWL0[15]}});

assign RBL1 = ~(mem_00 & {12{RWL1[0]}}) &
~(mem_01 & {12{RWL1[1]}}) &
~(mem_02 & {12{RWL1[2]}}) &
~(mem_03 & {12{RWL1[3]}}) &
~(mem_04 & {12{RWL1[4]}}) &
~(mem_05 & {12{RWL1[5]}}) &
~(mem_06 & {12{RWL1[6]}}) &
~(mem_07 & {12{RWL1[7]}}) &
~(mem_08 & {12{RWL1[8]}}) &
~(mem_09 & {12{RWL1[9]}}) &
~(mem_10 & {12{RWL1[10]}}) &
~(mem_11 & {12{RWL1[11]}}) &
~(mem_12 & {12{RWL1[12]}}) &
~(mem_13 & {12{RWL1[13]}}) &
~(mem_14 & {12{RWL1[14]}}) &
~(mem_15 & {12{RWL1[15]}});

always @(posedge WWL[0]) begin
mem_00 <= ~WBLb;
end

always @(posedge WWL[1]) begin
mem_01 <= ~WBLb;
end

always @(posedge WWL[2]) begin
mem_02 <= ~WBLb;
end

always @(posedge WWL[3]) begin
mem_03 <= ~WBLb;
end

always @(posedge WWL[4]) begin
mem_04 <= ~WBLb;
end

always @(posedge WWL[5]) begin
mem_05 <= ~WBLb;
end

always @(posedge WWL[6]) begin
mem_06 <= ~WBLb;
end

always @(posedge WWL[7]) begin
mem_07 <= ~WBLb;
end

always @(posedge WWL[8]) begin
mem_08 <= ~WBLb;
end

always @(posedge WWL[9]) begin
mem_09 <= ~WBLb;
end

always @(posedge WWL[10]) begin
mem_10 <= ~WBLb;
end

always @(posedge WWL[11]) begin
mem_11 <= ~WBLb;
end

always @(posedge WWL[12]) begin
mem_12 <= ~WBLb;
end

always @(posedge WWL[13]) begin
mem_13 <= ~WBLb;
end

always @(posedge WWL[14]) begin
mem_14 <= ~WBLb;
end

always @(posedge WWL[15]) begin
mem_15 <= ~WBLb;
end

// assert errors (multiwrite, etc.)

endmodule

389
rtl/src/array_shard/wordlines_comp.v
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@ -1,389 +0,0 @@
// © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions & limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make & use the physical chip.

// Wordline decodes
// Two versions:
// 12-in -> 64 one-hot (all selects, 1 comp used)
// 11-in -> 32 one-hot (half selects, 2 comps used)

`timescale 1 ps / 1 ps

// (c0)(12) -> 8 one-hots A0:A7
// (3)(45) -> 8 one-hots B0:B7
// A x B -> 64 one-hots W00:W63
module decode_wordlines_64 (

input c_na0,
input c_a0,
input na1_na2,
input na1_a2,
input a1_na2,
input a1_a2,
input na3,
input a3,
input na4_na5,
input na4_a5,
input a4_na5,
input a4_a5,
output [0:63] wl

);

wire [0:7] dcd_a_b;
wire [0:7] dcd_a;
wire [0:7] dcd_b_b;
wire [0:7] dcd_b;
wire [0:63] wl_b;

sky130_fd_sc_hd__nand2_2 DCD_A0b (.A(c_na0), .B(na1_na2), .X(dcd_a_b[0]));
sky130_fd_sc_hd__nand2_2 DCD_A1b (.A(c_na0), .B(na1_a2), .X(dcd_a_b[1]));
sky130_fd_sc_hd__nand2_2 DCD_A2b (.A(c_na0), .B(a1_na2), .X(dcd_a_b[2]));
sky130_fd_sc_hd__nand2_2 DCD_A3b (.A(c_na0), .B(a1_a2), .X(dcd_a_b[3]));
sky130_fd_sc_hd__nand2_2 DCD_A4b (.A(c_a0), .B(na1_na2), .X(dcd_a_b[4]));
sky130_fd_sc_hd__nand2_2 DCD_A5b (.A(c_a0), .B(na1_a2), .X(dcd_a_b[5]));
sky130_fd_sc_hd__nand2_2 DCD_A6b (.A(c_a0), .B(a1_na2), .X(dcd_a_b[6]));
sky130_fd_sc_hd__nand2_2 DCD_A7b (.A(c_a0), .B(a1_a2), .X(dcd_a_b[7]));

sky130_fd_sc_hd__inv_2 DCD_A0 (.A(dcd_a_b[0]), .Y(dcd_a[0]));
sky130_fd_sc_hd__inv_2 DCD_A1 (.A(dcd_a_b[1]), .Y(dcd_a[1]));
sky130_fd_sc_hd__inv_2 DCD_A2 (.A(dcd_a_b[2]), .Y(dcd_a[2]));
sky130_fd_sc_hd__inv_2 DCD_A3 (.A(dcd_a_b[3]), .Y(dcd_a[3]));
sky130_fd_sc_hd__inv_2 DCD_A4 (.A(dcd_a_b[4]), .Y(dcd_a[4]));
sky130_fd_sc_hd__inv_2 DCD_A5 (.A(dcd_a_b[5]), .Y(dcd_a[5]));
sky130_fd_sc_hd__inv_2 DCD_A6 (.A(dcd_a_b[6]), .Y(dcd_a[6]));
sky130_fd_sc_hd__inv_2 DCD_A7 (.A(dcd_a_b[7]), .Y(dcd_a[7]));

sky130_fd_sc_hd__nand2_2 DCD_B0b (.A(na3), .B(na4_na5), .X(dcd_b_b[0]));
sky130_fd_sc_hd__nand2_2 DCD_B1b (.A(na3), .B(na4_a5), .X(dcd_b_b[1]));
sky130_fd_sc_hd__nand2_2 DCD_B2b (.A(na3), .B(a4_na5), .X(dcd_b_b[2]));
sky130_fd_sc_hd__nand2_2 DCD_B3b (.A(na3), .B(a4_a5), .X(dcd_b_b[3]));
sky130_fd_sc_hd__nand2_2 DCD_B4b (.A(a3), .B(na4_na5), .X(dcd_b_b[4]));
sky130_fd_sc_hd__nand2_2 DCD_B5b (.A(a3), .B(na4_a5), .X(dcd_b_b[5]));
sky130_fd_sc_hd__nand2_2 DCD_B6b (.A(a3), .B(a4_na5), .X(dcd_b_b[6]));
sky130_fd_sc_hd__nand2_2 DCD_B7b (.A(a3), .B(a4_a5), .X(dcd_b_b[6]));

sky130_fd_sc_hd__inv_2 DCD_B0 (.A(dcd_b_b[0]), .Y(dcd_b[0]));
sky130_fd_sc_hd__inv_2 DCD_B1 (.A(dcd_b_b[1]), .Y(dcd_b[1]));
sky130_fd_sc_hd__inv_2 DCD_B2 (.A(dcd_b_b[2]), .Y(dcd_b[2]));
sky130_fd_sc_hd__inv_2 DCD_B3 (.A(dcd_b_b[3]), .Y(dcd_b[3]));
sky130_fd_sc_hd__inv_2 DCD_B4 (.A(dcd_b_b[4]), .Y(dcd_b[4]));
sky130_fd_sc_hd__inv_2 DCD_B5 (.A(dcd_b_b[5]), .Y(dcd_b[5]));
sky130_fd_sc_hd__inv_2 DCD_B6 (.A(dcd_b_b[6]), .Y(dcd_b[6]));
sky130_fd_sc_hd__inv_2 DCD_B7 (.A(dcd_b_b[7]), .Y(dcd_b[7]));

genvar i, j;
generate
for (i = 0; i < 8; i = i + 1) begin
for (j = 0; j < 8; j = j + 1) begin
sky130_fd_sc_hd__nand2_2 DCD_Cb (.A(dcd_a[i]), .B(dcd_b[j]), .X(wl_b[i*8+j]));
sky130_fd_sc_hd__inv_2 DCD_C (.A(wl_b[i*8+j]), .Y(wl[i*8+j]));
end
end
endgenerate

endmodule

// (c0)(12) -> 8 one-hots A0:A7
// (xa3)(45)-> 4 one-hots B0:B3 (xa3 is na3 for one decoder, a3 for the other)
// A x B -> 32 one-hots W00:W31
module decode_wordlines_32 (

input c_na0,
input c_a0,
input na1_na2,
input na1_a2,
input a1_na2,
input a1_a2,
input xa3,
input na4_na5,
input na4_a5,
input a4_na5,
input a4_a5,
output [0:31] wl

);

wire [0:7] dcd_a_b;
wire [0:7] dcd_a;
wire [0:3] dcd_b_b;
wire [0:3] dcd_b;
wire [0:31] wl_b;

sky130_fd_sc_hd__nand2_2 DCD_A0b (.A(c_na0), .B(na1_na2), .X(dcd_a_b[0]));
sky130_fd_sc_hd__nand2_2 DCD_A1b (.A(c_na0), .B(na1_a2), .X(dcd_a_b[1]));
sky130_fd_sc_hd__nand2_2 DCD_A2b (.A(c_na0), .B(a1_na2), .X(dcd_a_b[2]));
sky130_fd_sc_hd__nand2_2 DCD_A3b (.A(c_na0), .B(a1_a2), .X(dcd_a_b[3]));
sky130_fd_sc_hd__nand2_2 DCD_A4b (.A(c_a0), .B(na1_na2), .X(dcd_a_b[4]));
sky130_fd_sc_hd__nand2_2 DCD_A5b (.A(c_a0), .B(na1_a2), .X(dcd_a_b[5]));
sky130_fd_sc_hd__nand2_2 DCD_A6b (.A(c_a0), .B(a1_na2), .X(dcd_a_b[6]));
sky130_fd_sc_hd__nand2_2 DCD_A7b (.A(c_a0), .B(a1_a2), .X(dcd_a_b[7]));

sky130_fd_sc_hd__inv_2 DCD_A0 (.A(dcd_a_b[0]), .Y(dcd_a[0]));
sky130_fd_sc_hd__inv_2 DCD_A1 (.A(dcd_a_b[1]), .Y(dcd_a[1]));
sky130_fd_sc_hd__inv_2 DCD_A2 (.A(dcd_a_b[2]), .Y(dcd_a[2]));
sky130_fd_sc_hd__inv_2 DCD_A3 (.A(dcd_a_b[3]), .Y(dcd_a[3]));
sky130_fd_sc_hd__inv_2 DCD_A4 (.A(dcd_a_b[4]), .Y(dcd_a[4]));
sky130_fd_sc_hd__inv_2 DCD_A5 (.A(dcd_a_b[5]), .Y(dcd_a[5]));
sky130_fd_sc_hd__inv_2 DCD_A6 (.A(dcd_a_b[6]), .Y(dcd_a[6]));
sky130_fd_sc_hd__inv_2 DCD_A7 (.A(dcd_a_b[7]), .Y(dcd_a[7]));

sky130_fd_sc_hd__nand2_2 DCD_B0b (.A(xa3), .B(na4_na5), .X(dcd_b_b[0]));
sky130_fd_sc_hd__nand2_2 DCD_B1b (.A(xa3), .B(na4_a5), .X(dcd_b_b[1]));
sky130_fd_sc_hd__nand2_2 DCD_B2b (.A(xa3), .B(a4_na5), .X(dcd_b_b[2]));
sky130_fd_sc_hd__nand2_2 DCD_B3b (.A(xa3), .B(a4_a5), .X(dcd_b_b[3]));

sky130_fd_sc_hd__inv_2 DCD_B0 (.A(dcd_b_b[0]), .Y(dcd_b[0]));
sky130_fd_sc_hd__inv_2 DCD_B1 (.A(dcd_b_b[1]), .Y(dcd_b[1]));
sky130_fd_sc_hd__inv_2 DCD_B2 (.A(dcd_b_b[2]), .Y(dcd_b[2]));
sky130_fd_sc_hd__inv_2 DCD_B3 (.A(dcd_b_b[3]), .Y(dcd_b[3]));

genvar i, j;
generate
for (i = 0; i < 8; i = i + 1) begin
for (j = 0; j < 4; j = j + 1) begin
sky130_fd_sc_hd__nand2_2 DCD_Cb (.A(dcd_a[i]), .B(dcd_b[j]), .X(wl_b[i*4+j]));
sky130_fd_sc_hd__inv_2 DCD_C (.A(wl_b[i*4+j]), .Y(wl[i*4+j]));
end
end
endgenerate
endmodule

module wordlines_comp_64 (

input rd0_c_na0,
input rd0_c_a0,
input rd0_na1_na2,
input rd0_na1_a2,
input rd0_a1_na2,
input rd0_a1_a2,
input rd0_na3,
input rd0_a3,
input rd0_na4_na5,
input rd0_na4_a5,
input rd0_a4_na5,
input rd0_a4_a5,
output [0:63] rwl0_0,
output [0:63] rwl0_1,

input rd1_c_na0,
input rd1_c_a0,
input rd1_na1_na2,
input rd1_na1_a2,
input rd1_a1_na2,
input rd1_a1_a2,
input rd1_na3,
input rd1_a3,
input rd1_na4_na5,
input rd1_na4_a5,
input rd1_a4_na5,
input rd1_a4_a5,
output [0:63] rwl1_0,
output [0:63] rwl1_1,

input wr0_c_na0,
input wr0_c_a0,
input wr0_na1_na2,
input wr0_na1_a2,
input wr0_a1_na2,
input wr0_a1_a2,
input wr0_na3,
input wr0_a3,
input wr0_na4_na5,
input wr0_na4_a5,
input wr0_a4_na5,
input wr0_a4_a5,
output [0:63] wwl0_0,
output [0:63] wwl0_1

);

wire [0:63] rwl0;
wire [0:63] rwl1;
wire [0:63] wwl0;

// 64 wordlines per port
// if center sel is a0, 00:31 to left, 32:63 to right
// if center sel is a3, xxx0xx to left, xxx1xx to right

decode_wordlines_64 rd0 (
.c_na0(rd0_c_na0),
.c_a0(rd0_c_a0),
.na1_na2(rd0_na1_na2),
.na1_a2(rd0_na1_a2),
.a1_na2(rd0_a1_na2),
.a1_a2(rd0_a1_a2),
.na3(rd0_na3),
.a3(rd0_a3),
.na4_na5(rd0_na4_na5),
.na4_a5(rd0_na4_a5),
.a4_na5(rd0_a4_na5),
.a4_a5(rd0_a4_a5),
.wl(rwl0)
);

decode_wordlines_64 rd1 (
.c_na0(rd1_c_na0),
.c_a0(rd1_c_a0),
.na1_na2(rd1_na1_na2),
.na1_a2(rd1_na1_a2),
.a1_na2(rd1_a1_na2),
.a1_a2(rd1_a1_a2),
.na3(rd1_na3),
.a3(rd1_a3),
.na4_na5(rd1_na4_na5),
.na4_a5(rd1_na4_a5),
.a4_na5(rd1_a4_na5),
.a4_a5(rd1_a4_a5),
.wl(rwl1)
);

decode_wordlines_64 wr0 (
.c_na0(wr0_c_na0),
.c_a0(wr0_c_a0),
.na1_na2(wr0_na1_na2),
.na1_a2(wr0_na1_a2),
.a1_na2(wr0_a1_na2),
.a1_a2(wr0_a1_a2),
.na3(wr0_na3),
.a3(wr0_a3),
.na4_na5(wr0_na4_na5),
.na4_a5(wr0_na4_a5),
.a4_na5(wr0_a4_na5),
.a4_a5(wr0_a4_a5),
.wl(wwl0)
);

// add level for up/dn?
assign rwl0_0 = rwl0;
assign rwl0_1 = rwl0;
assign rwl1_0 = rwl1;
assign rwl1_1 = rwl1;
assign wwl0_0 = wwl0;
assign wwl0_1 = wwl0;

endmodule

module wordlines_comp_32 (

input rd0_c_na0,
input rd0_c_a0,
input rd0_na1_na2,
input rd0_na1_a2,
input rd0_a1_na2,
input rd0_a1_a2,
input rd0_xa3,
input rd0_na4_na5,
input rd0_na4_a5,
input rd0_a4_na5,
input rd0_a4_a5,
output [0:31] rwl0_0,
output [0:31] rwl0_1,

input rd1_c_na0,
input rd1_c_a0,
input rd1_na1_na2,
input rd1_na1_a2,
input rd1_a1_na2,
input rd1_a1_a2,
input rd1_xa3,
input rd1_na4_na5,
input rd1_na4_a5,
input rd1_a4_na5,
input rd1_a4_a5,
output [0:31] rwl1_0,
output [0:31] rwl1_1,

input wr0_c_na0,
input wr0_c_a0,
input wr0_na1_na2,
input wr0_na1_a2,
input wr0_a1_na2,
input wr0_a1_a2,
input wr0_xa3,
input wr0_na4_na5,
input wr0_na4_a5,
input wr0_a4_na5,
input wr0_a4_a5,
output [0:31] wwl0_0,
output [0:31] wwl0_1

);

wire [0:31] rwl0;
wire [0:31] rwl1;
wire [0:31] wwl0;

// 64 wordlines per port
// if center sel is a0, 00:31 to left, 32:63 to right
// if center sel is a3, xxx0xx to left, xxx1xx to right

decode_wordlines_32 rd0 (
.c_na0(rd0_c_na0),
.c_a0(rd0_c_a0),
.na1_na2(rd0_na1_na2),
.na1_a2(rd0_na1_a2),
.a1_na2(rd0_a1_na2),
.a1_a2(rd0_a1_a2),
.xa3(rd0_xa3),
.na4_na5(rd0_na4_na5),
.na4_a5(rd0_na4_a5),
.a4_na5(rd0_a4_na5),
.a4_a5(rd0_a4_a5),
.wl(rwl0)
);

decode_wordlines_32 rd1 (
.c_na0(rd1_c_na0),
.c_a0(rd1_c_a0),
.na1_na2(rd1_na1_na2),
.na1_a2(rd1_na1_a2),
.a1_na2(rd1_a1_na2),
.a1_a2(rd1_a1_a2),
.xa3(rd1_xa3),
.na4_na5(rd1_na4_na5),
.na4_a5(rd1_na4_a5),
.a4_na5(rd1_a4_na5),
.a4_a5(rd1_a4_a5),
.wl(rwl1)
);

decode_wordlines_32 wr0 (
.c_na0(wr0_c_na0),
.c_a0(wr0_c_a0),
.na1_na2(wr0_na1_na2),
.na1_a2(wr0_na1_a2),
.a1_na2(wr0_a1_na2),
.a1_a2(wr0_a1_a2),
.xa3(wr0_xa3),
.na4_na5(wr0_na4_na5),
.na4_a5(wr0_na4_a5),
.a4_na5(wr0_a4_na5),
.a4_a5(wr0_a4_a5),
.wl(wwl0)
);

// add level for up/dn?
assign rwl0_0 = rwl0;
assign rwl0_1 = rwl0;
assign rwl1_0 = rwl1;
assign rwl1_1 = rwl1;
assign wwl0_0 = wwl0;
assign wwl0_1 = wwl0;

endmodule

134
rtl/src/array_shard/wordlines_comp_32.v
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@ -0,0 +1,134 @@
// © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions & limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make & use the physical chip.

// Wordline decodes
// Two versions:
// 12-in -> 64 one-hot (all selects, 1 comp used)
// 11-in -> 32 one-hot (half selects, 2 comps used)

`timescale 1 ps / 1 ps

module wordlines_comp_32 (

input rd0_c_na0,
input rd0_c_a0,
input rd0_na1_na2,
input rd0_na1_a2,
input rd0_a1_na2,
input rd0_a1_a2,
input rd0_xa3,
input rd0_na4_na5,
input rd0_na4_a5,
input rd0_a4_na5,
input rd0_a4_a5,
output [0:31] rwl0_0,
output [0:31] rwl0_1,

input rd1_c_na0,
input rd1_c_a0,
input rd1_na1_na2,
input rd1_na1_a2,
input rd1_a1_na2,
input rd1_a1_a2,
input rd1_xa3,
input rd1_na4_na5,
input rd1_na4_a5,
input rd1_a4_na5,
input rd1_a4_a5,
output [0:31] rwl1_0,
output [0:31] rwl1_1,

input wr0_c_na0,
input wr0_c_a0,
input wr0_na1_na2,
input wr0_na1_a2,
input wr0_a1_na2,
input wr0_a1_a2,
input wr0_xa3,
input wr0_na4_na5,
input wr0_na4_a5,
input wr0_a4_na5,
input wr0_a4_a5,
output [0:31] wwl0_0,
output [0:31] wwl0_1

);

wire [0:31] rwl0;
wire [0:31] rwl1;
wire [0:31] wwl0;

// 64 wordlines per port
// if center sel is a0, 00:31 to left, 32:63 to right
// if center sel is a3, xxx0xx to left, xxx1xx to right

decode_wordlines_32 rd0 (
.c_na0(rd0_c_na0),
.c_a0(rd0_c_a0),
.na1_na2(rd0_na1_na2),
.na1_a2(rd0_na1_a2),
.a1_na2(rd0_a1_na2),
.a1_a2(rd0_a1_a2),
.xa3(rd0_xa3),
.na4_na5(rd0_na4_na5),
.na4_a5(rd0_na4_a5),
.a4_na5(rd0_a4_na5),
.a4_a5(rd0_a4_a5),
.wl(rwl0)
);

decode_wordlines_32 rd1 (
.c_na0(rd1_c_na0),
.c_a0(rd1_c_a0),
.na1_na2(rd1_na1_na2),
.na1_a2(rd1_na1_a2),
.a1_na2(rd1_a1_na2),
.a1_a2(rd1_a1_a2),
.xa3(rd1_xa3),
.na4_na5(rd1_na4_na5),
.na4_a5(rd1_na4_a5),
.a4_na5(rd1_a4_na5),
.a4_a5(rd1_a4_a5),
.wl(rwl1)
);

decode_wordlines_32 wr0 (
.c_na0(wr0_c_na0),
.c_a0(wr0_c_a0),
.na1_na2(wr0_na1_na2),
.na1_a2(wr0_na1_a2),
.a1_na2(wr0_a1_na2),
.a1_a2(wr0_a1_a2),
.xa3(wr0_xa3),
.na4_na5(wr0_na4_na5),
.na4_a5(wr0_na4_a5),
.a4_na5(wr0_a4_na5),
.a4_a5(wr0_a4_a5),
.wl(wwl0)
);

// add level for up/dn?
assign rwl0_0 = rwl0;
assign rwl0_1 = rwl0;
assign rwl1_0 = rwl1;
assign rwl1_1 = rwl1;
assign wwl0_0 = wwl0;
assign wwl0_1 = wwl0;

endmodule

140
rtl/src/array_shard/wordlines_comp_64.v
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// © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
// repository except in compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
// the work of authorship in physical form.
//
// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
// governing permissions & limitations under the License.
//
// Brief explanation of modifications:
//
// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
// it unambiguously permits a user to make & use the physical chip.

// Wordline decodes
// Two versions:
// 12-in -> 64 one-hot (all selects, 1 comp used)
// 11-in -> 32 one-hot (half selects, 2 comps used)

`timescale 1 ps / 1 ps

module wordlines_comp_64 (

input rd0_c_na0,
input rd0_c_a0,
input rd0_na1_na2,
input rd0_na1_a2,
input rd0_a1_na2,
input rd0_a1_a2,
input rd0_na3,
input rd0_a3,
input rd0_na4_na5,
input rd0_na4_a5,
input rd0_a4_na5,
input rd0_a4_a5,
output [0:63] rwl0_0,
output [0:63] rwl0_1,

input rd1_c_na0,
input rd1_c_a0,
input rd1_na1_na2,
input rd1_na1_a2,
input rd1_a1_na2,
input rd1_a1_a2,
input rd1_na3,
input rd1_a3,
input rd1_na4_na5,
input rd1_na4_a5,
input rd1_a4_na5,
input rd1_a4_a5,
output [0:63] rwl1_0,
output [0:63] rwl1_1,

input wr0_c_na0,
input wr0_c_a0,
input wr0_na1_na2,
input wr0_na1_a2,
input wr0_a1_na2,
input wr0_a1_a2,
input wr0_na3,
input wr0_a3,
input wr0_na4_na5,
input wr0_na4_a5,
input wr0_a4_na5,
input wr0_a4_a5,
output [0:63] wwl0_0,
output [0:63] wwl0_1

);

wire [0:63] rwl0;
wire [0:63] rwl1;
wire [0:63] wwl0;

// 64 wordlines per port
// if center sel is a0, 00:31 to left, 32:63 to right
// if center sel is a3, xxx0xx to left, xxx1xx to right

decode_wordlines_64 rd0 (
.c_na0(rd0_c_na0),
.c_a0(rd0_c_a0),
.na1_na2(rd0_na1_na2),
.na1_a2(rd0_na1_a2),
.a1_na2(rd0_a1_na2),
.a1_a2(rd0_a1_a2),
.na3(rd0_na3),
.a3(rd0_a3),
.na4_na5(rd0_na4_na5),
.na4_a5(rd0_na4_a5),
.a4_na5(rd0_a4_na5),
.a4_a5(rd0_a4_a5),
.wl(rwl0)
);

decode_wordlines_64 rd1 (
.c_na0(rd1_c_na0),
.c_a0(rd1_c_a0),
.na1_na2(rd1_na1_na2),
.na1_a2(rd1_na1_a2),
.a1_na2(rd1_a1_na2),
.a1_a2(rd1_a1_a2),
.na3(rd1_na3),
.a3(rd1_a3),
.na4_na5(rd1_na4_na5),
.na4_a5(rd1_na4_a5),
.a4_na5(rd1_a4_na5),
.a4_a5(rd1_a4_a5),
.wl(rwl1)
);

decode_wordlines_64 wr0 (
.c_na0(wr0_c_na0),
.c_a0(wr0_c_a0),
.na1_na2(wr0_na1_na2),
.na1_a2(wr0_na1_a2),
.a1_na2(wr0_a1_na2),
.a1_a2(wr0_a1_a2),
.na3(wr0_na3),
.a3(wr0_a3),
.na4_na5(wr0_na4_na5),
.na4_a5(wr0_na4_a5),
.a4_na5(wr0_a4_na5),
.a4_a5(wr0_a4_a5),
.wl(wwl0)
);

// add level for up/dn?
assign rwl0_0 = rwl0;
assign rwl0_1 = rwl0;
assign rwl1_0 = rwl1;
assign rwl1_1 = rwl1;
assign wwl0_0 = wwl0;
assign wwl0_1 = wwl0;

endmodule

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rtl/src/site/osc.v
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