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// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions & limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make & use the physical chip.
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`timescale 1 ps / 1 ps
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// I/O pins/logic
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// put address here for now so wires route through it
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module inout_comp (
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input rd0_c_na0,
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input rd0_c_a0,
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input rd0_na1_na2,
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input rd0_na1_a2,
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input rd0_a1_na2,
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input rd0_a1_a2,
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input rd0_na3,
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input rd0_a3,
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input rd0_na4_na5,
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input rd0_na4_a5,
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input rd0_a4_na5,
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input rd0_a4_a5,
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input rd1_c_na0,
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input rd1_c_a0,
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input rd1_na1_na2,
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input rd1_na1_a2,
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input rd1_a1_na2,
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input rd1_a1_a2,
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input rd1_na3,
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input rd1_a3,
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input rd1_na4_na5,
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input rd1_na4_a5,
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input rd1_a4_na5,
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input rd1_a4_a5,
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input wr0_c_na0,
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input wr0_c_a0,
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input wr0_na1_na2,
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input wr0_na1_a2,
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input wr0_a1_na2,
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input wr0_a1_a2,
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input wr0_na3,
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input wr0_a3,
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input wr0_na4_na5,
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input wr0_na4_a5,
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input wr0_a4_na5,
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input wr0_a4_a5,
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output rd0_c_na0_i,
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output rd0_c_a0_i,
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output rd0_na1_na2_i,
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output rd0_na1_a2_i,
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output rd0_a1_na2_i,
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output rd0_a1_a2_i,
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output rd0_na3_i,
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output rd0_a3_i,
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output rd0_na4_na5_i,
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output rd0_na4_a5_i,
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output rd0_a4_na5_i,
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output rd0_a4_a5_i,
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output rd1_c_na0_i,
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output rd1_c_a0_i,
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output rd1_na1_na2_i,
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output rd1_na1_a2_i,
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output rd1_a1_na2_i,
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output rd1_a1_a2_i,
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output rd1_na3_i,
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output rd1_a3_i,
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output rd1_na4_na5_i,
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output rd1_na4_a5_i,
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output rd1_a4_na5_i,
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output rd1_a4_a5_i,
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output wr0_c_na0_i,
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output wr0_c_a0_i,
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output wr0_na1_na2_i,
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output wr0_na1_a2_i,
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output wr0_a1_na2_i,
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output wr0_a1_a2_i,
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output wr0_na3_i,
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output wr0_a3_i,
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output wr0_na4_na5_i,
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output wr0_na4_a5_i,
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output wr0_a4_na5_i,
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output wr0_a4_a5_i,
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input [0:11] rd0_dat_0x0,
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input [0:11] rd0_dat_0x1,
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input [0:11] rd0_dat_1x0,
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input [0:11] rd0_dat_1x1,
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output [0:23] rd0_dat,
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input [0:11] rd1_dat_0x0,
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input [0:11] rd1_dat_0x1,
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input [0:11] rd1_dat_1x0,
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input [0:11] rd1_dat_1x1,
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output [0:23] rd1_dat,
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input [0:23] wr0_dat,
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output [0:11] wr0_dat_0x0,
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output [0:11] wr0_dat_b_0x0,
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output [0:11] wr0_dat_0x1,
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output [0:11] wr0_dat_b_0x1,
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output [0:11] wr0_dat_1x0,
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output [0:11] wr0_dat_b_1x0,
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output [0:11] wr0_dat_1x1,
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output [0:11] wr0_dat_b_1x1
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);
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assign rd0_c_na0_i = rd0_c_na0;
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assign rd0_c_a0_i = rd0_c_a0;
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assign rd0_na1_na2_i = rd0_na1_na2;
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assign rd0_na1_a2_i = rd0_na1_a2;
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assign rd0_a1_na2_i = rd0_a1_na2;
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assign rd0_a1_a2_i = rd0_a1_a2;
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assign rd0_na3_i = rd0_na3;
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assign rd0_a3_i = rd0_a3;
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assign rd0_na4_na5_i = rd0_na4_na5;
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assign rd0_na4_a5_i = rd0_na4_a5;
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assign rd0_a4_na5_i = rd0_a4_na5;
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assign rd0_a4_a5_i = rd0_a4_a5;
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// dot-or then buf?
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assign rd0_dat = {rd0_dat_0x0 | rd0_dat_1x0, rd0_dat_0x1 | rd0_dat_1x1};
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assign rd1_dat = {rd1_dat_0x0 | rd1_dat_1x0, rd1_dat_0x1 | rd1_dat_1x1};
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genvar i;
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for (i = 0; i < 12; i = i + 1) begin
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sky130_fd_sc_hd__buf_1 BUF_0 (.A(wr0_dat[i]), .X(wr0_dat_0x0[i]));
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sky130_fd_sc_hd__inv_1 INV_0 (.A(wr0_dat[i]), .Y(wr0_dat_b_0x0[i]));
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sky130_fd_sc_hd__buf_1 BUF_1 (.A(wr0_dat[i]), .X(wr0_dat_1x0[i]));
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sky130_fd_sc_hd__inv_1 INV_1 (.A(wr0_dat[i]), .Y(wr0_dat_b_1x0[i]));
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end
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for (i = 0; i < 12; i = i + 1) begin
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sky130_fd_sc_hd__buf_1 BUF_0 (.A(wr0_dat[i+12]), .X(wr0_dat_0x1[i]));
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sky130_fd_sc_hd__inv_1 INV_0 (.A(wr0_dat[i+12]), .Y(wr0_dat_b_0x1[i]));
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sky130_fd_sc_hd__buf_1 BUF_1 (.A(wr0_dat[i+12]), .X(wr0_dat_1x1[i]));
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sky130_fd_sc_hd__inv_1 INV_1 (.A(wr0_dat[i+12]), .Y(wr0_dat_b_1x1[i]));
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end
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endmodule
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