toy-sram/rtl/sim
openpowerwtf f9d5f06f61 init
..
coco init
python init
gtkwave.vcd init
readme.md init
sim init
sim.txt init
src init
wtf.gtkw init
wtf_ddr.gtkw init

readme.md

Functional verification of array and site logic

CURRENT (cocotb+iverilog)

OLD (pyverilator)

check rtl

verilator --lint-only -Isrc -Wno-LITENDIAN src/test_ra_sdr.v

build/sim

not working at all with verilator v4.210

sim -m sdr -c 1000 -t