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toy-sram/rtl/sim/gtkwave.vcd

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$version Generated by VerilatedVcd $end
$date Wed Aug 18 08:17:30 2021
$end
$timescale 1ns $end
$scope module TOP $end
$var wire 32 g* bist_ctl [0:31] $end
$var wire 32 o* bist_status [0:31] $end
$var wire 16 _* cfg_dat [0:15] $end
$var wire 1 W* cfg_wr $end
$var wire 1 ?* clk $end
$var wire 1 G* clk2x $end
$var wire 6 !+ rd_adr_0 [0:5] $end
$var wire 6 I+ rd_adr_1 [0:5] $end
$var wire 6 q+ rd_adr_2 [0:5] $end
$var wire 6 ;, rd_adr_3 [0:5] $end
$var wire 72 )+ rd_dat_0 [0:71] $end
$var wire 72 Q+ rd_dat_1 [0:71] $end
$var wire 72 y+ rd_dat_2 [0:71] $end
$var wire 72 C, rd_dat_3 [0:71] $end
$var wire 1 w* rd_enb_0 $end
$var wire 1 A+ rd_enb_1 $end
$var wire 1 i+ rd_enb_2 $end
$var wire 1 3, rd_enb_3 $end
$var wire 1 O* reset $end
$var wire 6 c, wr_adr_0 [0:5] $end
$var wire 6 -- wr_adr_1 [0:5] $end
$var wire 72 k, wr_dat_0 [0:71] $end
$var wire 72 5- wr_dat_1 [0:71] $end
$var wire 1 [, wr_enb_0 $end
$var wire 1 %- wr_enb_1 $end
$scope module test_ra_ddr $end
$var wire 32 g* bist_ctl [0:31] $end
$var wire 32 o* bist_status [0:31] $end
$var wire 16 g& cfg [0:15] $end
$var wire 16 _* cfg_dat [0:15] $end
$var wire 1 W* cfg_wr $end
$var wire 1 ?* clk $end
$var wire 1 G* clk2x $end
$var wire 1 7* el_sel $end
$var wire 6 U- mux_rd0_adr [0:5] $end
$var wire 1 M- mux_rd0_enb $end
$var wire 6 e- mux_rd1_adr [0:5] $end
$var wire 1 ]- mux_rd1_enb $end
$var wire 6 u- mux_rd2_adr [0:5] $end
$var wire 1 m- mux_rd2_enb $end
$var wire 6 '. mux_rd3_adr [0:5] $end
$var wire 1 }- mux_rd3_enb $end
$var wire 6 7. mux_wr0_adr [0:5] $end
$var wire 72 ?. mux_wr0_dat [0:71] $end
$var wire 1 /. mux_wr0_enb $end
$var wire 6 _. mux_wr1_adr [0:5] $end
$var wire 72 g. mux_wr1_dat [0:71] $end
$var wire 1 W. mux_wr1_enb $end
$var wire 6 !+ rd_adr_0 [0:5] $end
$var wire 6 I+ rd_adr_1 [0:5] $end
$var wire 6 q+ rd_adr_2 [0:5] $end
$var wire 6 ;, rd_adr_3 [0:5] $end
$var wire 72 )+ rd_dat_0 [0:71] $end
$var wire 72 Q+ rd_dat_1 [0:71] $end
$var wire 72 y+ rd_dat_2 [0:71] $end
$var wire 72 C, rd_dat_3 [0:71] $end
$var wire 1 w* rd_enb_0 $end
$var wire 1 A+ rd_enb_1 $end
$var wire 1 i+ rd_enb_2 $end
$var wire 1 3, rd_enb_3 $end
$var wire 1 O* reset $end
$var wire 1 # strobe $end
$var wire 6 c, wr_adr_0 [0:5] $end
$var wire 6 -- wr_adr_1 [0:5] $end
$var wire 72 k, wr_dat_0 [0:71] $end
$var wire 72 5- wr_dat_1 [0:71] $end
$var wire 1 [, wr_enb_0 $end
$var wire 1 %- wr_enb_1 $end
$scope module bist $end
$var wire 32 1/ GENMODE [31:0] $end
$var wire 1 )' active $end
$var wire 6 i/ bist_rd0_adr [0:5] $end
$var wire 1 a/ bist_rd0_enb $end
$var wire 6 y/ bist_rd1_adr [0:5] $end
$var wire 1 q/ bist_rd1_enb $end
$var wire 6 +0 bist_rd2_adr [0:5] $end
$var wire 1 #0 bist_rd2_enb $end
$var wire 6 ;0 bist_rd3_adr [0:5] $end
$var wire 1 30 bist_rd3_enb $end
$var wire 6 K0 bist_wr0_adr [0:5] $end
$var wire 72 S0 bist_wr0_dat [0:71] $end
$var wire 1 C0 bist_wr0_enb $end
$var wire 6 s0 bist_wr1_adr [0:5] $end
$var wire 72 {0 bist_wr1_dat [0:71] $end
$var wire 1 k0 bist_wr1_enb $end
$var wire 1 ?* clk $end
$var wire 32 g* ctl [0:31] $end
$var wire 6 !+ rd0_adr_in [0:5] $end
$var wire 6 U- rd0_adr_out [0:5] $end
$var wire 72 )+ rd0_dat [0:71] $end
$var wire 1 w* rd0_enb_in $end
$var wire 1 M- rd0_enb_out $end
$var wire 6 I+ rd1_adr_in [0:5] $end
$var wire 6 e- rd1_adr_out [0:5] $end
$var wire 72 Q+ rd1_dat [0:71] $end
$var wire 1 A+ rd1_enb_in $end
$var wire 1 ]- rd1_enb_out $end
$var wire 6 q+ rd2_adr_in [0:5] $end
$var wire 6 u- rd2_adr_out [0:5] $end
$var wire 72 y+ rd2_dat [0:71] $end
$var wire 1 i+ rd2_enb_in $end
$var wire 1 m- rd2_enb_out $end
$var wire 6 ;, rd3_adr_in [0:5] $end
$var wire 6 '. rd3_adr_out [0:5] $end
$var wire 72 C, rd3_dat [0:71] $end
$var wire 1 3, rd3_enb_in $end
$var wire 1 }- rd3_enb_out $end
$var wire 1 O* reset $end
$var wire 6 !' seq_d [0:5] $end
$var wire 6 !' seq_q [0:5] $end
$var wire 32 o* status [0:31] $end
$var wire 6 c, wr0_adr_in [0:5] $end
$var wire 6 7. wr0_adr_out [0:5] $end
$var wire 72 k, wr0_dat_in [0:71] $end
$var wire 72 ?. wr0_dat_out [0:71] $end
$var wire 1 [, wr0_enb_in $end
$var wire 1 /. wr0_enb_out $end
$var wire 6 -- wr1_adr_in [0:5] $end
$var wire 6 _. wr1_adr_out [0:5] $end
$var wire 72 5- wr1_dat_in [0:71] $end
$var wire 72 g. wr1_dat_out [0:71] $end
$var wire 1 %- wr1_enb_in $end
$var wire 1 W. wr1_enb_out $end
$upscope $end
$scope module cfig $end
$var wire 32 1/ GENMODE [31:0] $end
$var wire 32 Y/ INIT [31:0] $end
$var wire 32 w& cfg [0:31] $end
$var wire 32 )/ cfg_d [0:31] $end
$var wire 32 !/ cfg_dat [0:31] $end
$var wire 32 w& cfg_q [0:31] $end
$var wire 1 W* cfg_wr $end
$var wire 1 ?* clk $end
$var wire 1 O* reset $end
$upscope $end
$scope module lcb $end
$var wire 32 1/ GENMODE [31:0] $end
$var wire 32 o& cfg [0:31] $end
$var wire 1 G* clk $end
$var wire 1 9/ clk_dly $end
$var wire 1 Q/ clk_dly2 $end
$var wire 1 7* el_sel $end
$var wire 1 7* el_sel_q $end
$var wire 1 A/ o0 $end
$var wire 1 I/ o1 $end
$var wire 1 O* reset $end
$var wire 1 # strobe $end
$upscope $end
$scope module ra $end
$var wire 32 1/ GENMODE [31:0] $end
$var wire 1 ?* clk $end
$var wire 1 7* el_sel $end
$var wire 72 -! ra_rd_dat_0 [0:71] $end
$var wire 72 G" ra_rd_dat_1 [0:71] $end
$var wire 72 72 ra_rd_dat_2 [0:71] $end
$var wire 72 Q3 ra_rd_dat_3 [0:71] $end
$var wire 6 q3 ra_wr_adr_0 [0:5] $end
$var wire 6 %5 ra_wr_adr_1 [0:5] $end
$var wire 1 i3 ra_wr_enb_0 $end
$var wire 1 {4 ra_wr_enb_1 $end
$var wire 1 S rd0_a1_a2 $end
$var wire 1 K rd0_a1_na2 $end
$var wire 1 c rd0_a3 $end
$var wire 1 %! rd0_a4_a5 $end
$var wire 1 { rd0_a4_na5 $end
$var wire 1 3 rd0_c_a0 $end
$var wire 1 + rd0_c_na0 $end
$var wire 1 C rd0_na1_a2 $end
$var wire 1 ; rd0_na1_na2 $end
$var wire 1 [ rd0_na3 $end
$var wire 1 s rd0_na4_a5 $end
$var wire 1 k rd0_na4_na5 $end
$var wire 1 m! rd1_a1_a2 $end
$var wire 1 e! rd1_a1_na2 $end
$var wire 1 }! rd1_a3 $end
$var wire 1 ?" rd1_a4_a5 $end
$var wire 1 7" rd1_a4_na5 $end
$var wire 1 M! rd1_c_a0 $end
$var wire 1 E! rd1_c_na0 $end
$var wire 1 ]! rd1_na1_a2 $end
$var wire 1 U! rd1_na1_na2 $end
$var wire 1 u! rd1_na3 $end
$var wire 1 /" rd1_na4_a5 $end
$var wire 1 '" rd1_na4_na5 $end
$var wire 1 ]1 rd2_a1_a2 $end
$var wire 1 U1 rd2_a1_na2 $end
$var wire 1 m1 rd2_a3 $end
$var wire 1 /2 rd2_a4_a5 $end
$var wire 1 '2 rd2_a4_na5 $end
$var wire 1 =1 rd2_c_a0 $end
$var wire 1 51 rd2_c_na0 $end
$var wire 1 M1 rd2_na1_a2 $end
$var wire 1 E1 rd2_na1_na2 $end
$var wire 1 e1 rd2_na3 $end
$var wire 1 }1 rd2_na4_a5 $end
$var wire 1 u1 rd2_na4_na5 $end
$var wire 1 w2 rd3_a1_a2 $end
$var wire 1 o2 rd3_a1_na2 $end
$var wire 1 )3 rd3_a3 $end
$var wire 1 I3 rd3_a4_a5 $end
$var wire 1 A3 rd3_a4_na5 $end
$var wire 1 W2 rd3_c_a0 $end
$var wire 1 O2 rd3_c_na0 $end
$var wire 1 g2 rd3_na1_a2 $end
$var wire 1 _2 rd3_na1_na2 $end
$var wire 1 !3 rd3_na3 $end
$var wire 1 93 rd3_na4_a5 $end
$var wire 1 13 rd3_na4_na5 $end
$var wire 6 U- rd_adr_0 [0:5] $end
$var wire 6 i# rd_adr_02 [0:5] $end
$var wire 6 9' rd_adr_0_q [0:5] $end
$var wire 6 e- rd_adr_1 [0:5] $end
$var wire 6 y# rd_adr_13 [0:5] $end
$var wire 6 a' rd_adr_1_q [0:5] $end
$var wire 6 u- rd_adr_2 [0:5] $end
$var wire 6 +( rd_adr_2_q [0:5] $end
$var wire 6 '. rd_adr_3 [0:5] $end
$var wire 6 ;( rd_adr_3_q [0:5] $end
$var wire 72 )+ rd_dat_0 [0:71] $end
$var wire 72 A' rd_dat_0_hold_q [0:71] $end
$var wire 72 5) rd_dat_0_q [0:71] $end
$var wire 72 Q+ rd_dat_1 [0:71] $end
$var wire 72 i' rd_dat_1_hold_q [0:71] $end
$var wire 72 M) rd_dat_1_q [0:71] $end
$var wire 72 y+ rd_dat_2 [0:71] $end
$var wire 72 e) rd_dat_2_q [0:71] $end
$var wire 72 C, rd_dat_3 [0:71] $end
$var wire 72 }) rd_dat_3_q [0:71] $end
$var wire 1 M- rd_enb_0 $end
$var wire 1 a# rd_enb_02 $end
$var wire 1 1' rd_enb_0_q $end
$var wire 1 ]- rd_enb_1 $end
$var wire 1 q# rd_enb_13 $end
$var wire 1 Y' rd_enb_1_q $end
$var wire 1 m- rd_enb_2 $end
$var wire 1 #( rd_enb_2_q $end
$var wire 1 }- rd_enb_3 $end
$var wire 1 3( rd_enb_3_q $end
$var wire 1 O* reset $end
$var wire 1 # strobe $end
$var wire 1 -5 strobe_int $end
$var wire 1 )# wr0_a1_a2 $end
$var wire 1 !# wr0_a1_na2 $end
$var wire 1 9# wr0_a3 $end
$var wire 1 Y# wr0_a4_a5 $end
$var wire 1 Q# wr0_a4_na5 $end
$var wire 1 g" wr0_c_a0 $end
$var wire 1 _" wr0_c_na0 $end
$var wire 1 w" wr0_na1_a2 $end
$var wire 1 o" wr0_na1_na2 $end
$var wire 1 1# wr0_na3 $end
$var wire 1 I# wr0_na4_a5 $end
$var wire 1 A# wr0_na4_na5 $end
$var wire 1 C4 wr1_a1_a2 $end
$var wire 1 ;4 wr1_a1_na2 $end
$var wire 1 S4 wr1_a3 $end
$var wire 1 s4 wr1_a4_a5 $end
$var wire 1 k4 wr1_a4_na5 $end
$var wire 1 #4 wr1_c_a0 $end
$var wire 1 y3 wr1_c_na0 $end
$var wire 1 34 wr1_na1_a2 $end
$var wire 1 +4 wr1_na1_na2 $end
$var wire 1 K4 wr1_na3 $end
$var wire 1 c4 wr1_na4_a5 $end
$var wire 1 [4 wr1_na4_na5 $end
$var wire 6 7. wr_adr_0 [0:5] $end
$var wire 6 +$ wr_adr_01 [0:5] $end
$var wire 6 K( wr_adr_0_q [0:5] $end
$var wire 6 _. wr_adr_1 [0:5] $end
$var wire 6 s( wr_adr_1_q [0:5] $end
$var wire 72 ?. wr_dat_0 [0:71] $end
$var wire 72 3$ wr_dat_01 [0:71] $end
$var wire 72 S( wr_dat_0_q [0:71] $end
$var wire 72 g. wr_dat_1 [0:71] $end
$var wire 72 {( wr_dat_1_q [0:71] $end
$var wire 1 /. wr_enb_0 $end
$var wire 1 #$ wr_enb_01 $end
$var wire 1 C( wr_enb_0_q $end
$var wire 1 W. wr_enb_1 $end
$var wire 1 k( wr_enb_1_q $end
$scope module add_clk $end
$var wire 32 1/ GENMODE [31:0] $end
$var wire 1 S rd0_a1_a2 $end
$var wire 1 K rd0_a1_na2 $end
$var wire 1 c rd0_a3 $end
$var wire 1 %! rd0_a4_a5 $end
$var wire 1 { rd0_a4_na5 $end
$var wire 1 3 rd0_c_a0 $end
$var wire 1 + rd0_c_na0 $end
$var wire 1 C rd0_na1_a2 $end
$var wire 1 ; rd0_na1_na2 $end
$var wire 1 [ rd0_na3 $end
$var wire 1 s rd0_na4_a5 $end
$var wire 1 k rd0_na4_na5 $end
$var wire 1 m! rd1_a1_a2 $end
$var wire 1 e! rd1_a1_na2 $end
$var wire 1 }! rd1_a3 $end
$var wire 1 ?" rd1_a4_a5 $end
$var wire 1 7" rd1_a4_na5 $end
$var wire 1 M! rd1_c_a0 $end
$var wire 1 E! rd1_c_na0 $end
$var wire 1 ]! rd1_na1_a2 $end
$var wire 1 U! rd1_na1_na2 $end
$var wire 1 u! rd1_na3 $end
$var wire 1 /" rd1_na4_a5 $end
$var wire 1 '" rd1_na4_na5 $end
$var wire 6 i# rd_adr_0 [0:5] $end
$var wire 6 y# rd_adr_1 [0:5] $end
$var wire 1 a# rd_enb_0 $end
$var wire 1 q# rd_enb_1 $end
$var wire 1 -5 strobe $end
$var wire 1 )# wr0_a1_a2 $end
$var wire 1 !# wr0_a1_na2 $end
$var wire 1 9# wr0_a3 $end
$var wire 1 Y# wr0_a4_a5 $end
$var wire 1 Q# wr0_a4_na5 $end
$var wire 1 g" wr0_c_a0 $end
$var wire 1 _" wr0_c_na0 $end
$var wire 1 w" wr0_na1_a2 $end
$var wire 1 o" wr0_na1_na2 $end
$var wire 1 1# wr0_na3 $end
$var wire 1 I# wr0_na4_a5 $end
$var wire 1 A# wr0_na4_na5 $end
$var wire 6 +$ wr_adr_0 [0:5] $end
$var wire 1 #$ wr_enb_0 $end
$scope module predecode_r0 $end
$var wire 1 S a1_a2 $end
$var wire 1 K a1_na2 $end
$var wire 1 c a3 $end
$var wire 1 %! a4_a5 $end
$var wire 1 { a4_na5 $end
$var wire 6 i# address [0:5] $end
$var wire 1 3 c_a0 $end
$var wire 1 + c_na0 $end
$var wire 1 a# clock_enable $end
$var wire 1 a# enable $end
$var wire 6 K$ inv_address [0:5] $end
$var wire 1 ]5 n_a1_a2 $end
$var wire 1 U5 n_a1_na2 $end
$var wire 1 }5 n_a4_a5 $end
$var wire 1 u5 n_a4_na5 $end
$var wire 1 =5 n_c_a0 $end
$var wire 1 55 n_c_na0 $end
$var wire 1 M5 n_na1_a2 $end
$var wire 1 E5 n_na1_na2 $end
$var wire 1 m5 n_na4_a5 $end
$var wire 1 e5 n_na4_na5 $end
$var wire 1 C na1_a2 $end
$var wire 1 ; na1_na2 $end
$var wire 1 [ na3 $end
$var wire 1 s na4_a5 $end
$var wire 1 k na4_na5 $end
$var wire 1 -5 strobe $end
$upscope $end
$scope module predecode_r1 $end
$var wire 1 m! a1_a2 $end
$var wire 1 e! a1_na2 $end
$var wire 1 }! a3 $end
$var wire 1 ?" a4_a5 $end
$var wire 1 7" a4_na5 $end
$var wire 6 y# address [0:5] $end
$var wire 1 M! c_a0 $end
$var wire 1 E! c_na0 $end
$var wire 1 q# clock_enable $end
$var wire 1 q# enable $end
$var wire 6 S$ inv_address [0:5] $end
$var wire 1 O6 n_a1_a2 $end
$var wire 1 G6 n_a1_na2 $end
$var wire 1 o6 n_a4_a5 $end
$var wire 1 g6 n_a4_na5 $end
$var wire 1 /6 n_c_a0 $end
$var wire 1 '6 n_c_na0 $end
$var wire 1 ?6 n_na1_a2 $end
$var wire 1 76 n_na1_na2 $end
$var wire 1 _6 n_na4_a5 $end
$var wire 1 W6 n_na4_na5 $end
$var wire 1 ]! na1_a2 $end
$var wire 1 U! na1_na2 $end
$var wire 1 u! na3 $end
$var wire 1 /" na4_a5 $end
$var wire 1 '" na4_na5 $end
$var wire 1 -5 strobe $end
$upscope $end
$scope module predecode_w0 $end
$var wire 1 )# a1_a2 $end
$var wire 1 !# a1_na2 $end
$var wire 1 9# a3 $end
$var wire 1 Y# a4_a5 $end
$var wire 1 Q# a4_na5 $end
$var wire 6 +$ address [0:5] $end
$var wire 1 g" c_a0 $end
$var wire 1 _" c_na0 $end
$var wire 1 #$ clock_enable $end
$var wire 1 #$ enable $end
$var wire 6 [$ inv_address [0:5] $end
$var wire 1 A7 n_a1_a2 $end
$var wire 1 97 n_a1_na2 $end
$var wire 1 a7 n_a4_a5 $end
$var wire 1 Y7 n_a4_na5 $end
$var wire 1 !7 n_c_a0 $end
$var wire 1 w6 n_c_na0 $end
$var wire 1 17 n_na1_a2 $end
$var wire 1 )7 n_na1_na2 $end
$var wire 1 Q7 n_na4_a5 $end
$var wire 1 I7 n_na4_na5 $end
$var wire 1 w" na1_a2 $end
$var wire 1 o" na1_na2 $end
$var wire 1 1# na3 $end
$var wire 1 I# na4_a5 $end
$var wire 1 A# na4_na5 $end
$var wire 1 -5 strobe $end
$upscope $end
$upscope $end
$scope module array0 $end
$var wire 1 3 rd0_a0 $end
$var wire 1 5% rd0_a1 $end
$var wire 1 S rd0_a1_a2 $end
$var wire 1 K rd0_a1_na2 $end
$var wire 1 =% rd0_a2 $end
$var wire 1 c rd0_a3 $end
$var wire 1 E% rd0_a4 $end
$var wire 1 %! rd0_a4_a5 $end
$var wire 1 { rd0_a4_na5 $end
$var wire 1 M% rd0_a5 $end
$var wire 1 3 rd0_c_a0 $end
$var wire 1 + rd0_c_na0 $end
$var wire 1 %% rd0_enable $end
$var wire 1 C rd0_na1_a2 $end
$var wire 1 ; rd0_na1_na2 $end
$var wire 1 [ rd0_na3 $end
$var wire 1 s rd0_na4_a5 $end
$var wire 1 k rd0_na4_na5 $end
$var wire 1 M! rd1_a0 $end
$var wire 1 U% rd1_a1 $end
$var wire 1 m! rd1_a1_a2 $end
$var wire 1 e! rd1_a1_na2 $end
$var wire 1 ]% rd1_a2 $end
$var wire 1 }! rd1_a3 $end
$var wire 1 e% rd1_a4 $end
$var wire 1 ?" rd1_a4_a5 $end
$var wire 1 7" rd1_a4_na5 $end
$var wire 1 m% rd1_a5 $end
$var wire 1 M! rd1_c_a0 $end
$var wire 1 E! rd1_c_na0 $end
$var wire 1 -% rd1_enable $end
$var wire 1 ]! rd1_na1_a2 $end
$var wire 1 U! rd1_na1_na2 $end
$var wire 1 u! rd1_na3 $end
$var wire 1 /" rd1_na4_a5 $end
$var wire 1 '" rd1_na4_na5 $end
$var wire 24 c$ rd_dat_0 [0:23] $end
$var wire 24 k$ rd_dat_1 [0:23] $end
$var wire 1 g" wr0_a0 $end
$var wire 1 u% wr0_a1 $end
$var wire 1 )# wr0_a1_a2 $end
$var wire 1 !# wr0_a1_na2 $end
$var wire 1 }% wr0_a2 $end
$var wire 1 9# wr0_a3 $end
$var wire 1 '& wr0_a4 $end
$var wire 1 Y# wr0_a4_a5 $end
$var wire 1 Q# wr0_a4_na5 $end
$var wire 1 /& wr0_a5 $end
$var wire 1 g" wr0_c_a0 $end
$var wire 1 _" wr0_c_na0 $end
$var wire 1 {$ wr0_enable $end
$var wire 1 w" wr0_na1_a2 $end
$var wire 1 o" wr0_na1_na2 $end
$var wire 1 1# wr0_na3 $end
$var wire 1 I# wr0_na4_a5 $end
$var wire 1 A# wr0_na4_na5 $end
$var wire 24 s$ wr_dat_0 [0:23] $end
$upscope $end
$scope module array1 $end
$var wire 1 3 rd0_a0 $end
$var wire 1 5% rd0_a1 $end
$var wire 1 S rd0_a1_a2 $end
$var wire 1 K rd0_a1_na2 $end
$var wire 1 =% rd0_a2 $end
$var wire 1 c rd0_a3 $end
$var wire 1 E% rd0_a4 $end
$var wire 1 %! rd0_a4_a5 $end
$var wire 1 { rd0_a4_na5 $end
$var wire 1 M% rd0_a5 $end
$var wire 1 3 rd0_c_a0 $end
$var wire 1 + rd0_c_na0 $end
$var wire 1 %% rd0_enable $end
$var wire 1 C rd0_na1_a2 $end
$var wire 1 ; rd0_na1_na2 $end
$var wire 1 [ rd0_na3 $end
$var wire 1 s rd0_na4_a5 $end
$var wire 1 k rd0_na4_na5 $end
$var wire 1 M! rd1_a0 $end
$var wire 1 U% rd1_a1 $end
$var wire 1 m! rd1_a1_a2 $end
$var wire 1 e! rd1_a1_na2 $end
$var wire 1 ]% rd1_a2 $end
$var wire 1 }! rd1_a3 $end
$var wire 1 e% rd1_a4 $end
$var wire 1 ?" rd1_a4_a5 $end
$var wire 1 7" rd1_a4_na5 $end
$var wire 1 m% rd1_a5 $end
$var wire 1 M! rd1_c_a0 $end
$var wire 1 E! rd1_c_na0 $end
$var wire 1 -% rd1_enable $end
$var wire 1 ]! rd1_na1_a2 $end
$var wire 1 U! rd1_na1_na2 $end
$var wire 1 u! rd1_na3 $end
$var wire 1 /" rd1_na4_a5 $end
$var wire 1 '" rd1_na4_na5 $end
$var wire 24 7& rd_dat_0 [0:23] $end
$var wire 24 ?& rd_dat_1 [0:23] $end
$var wire 1 g" wr0_a0 $end
$var wire 1 u% wr0_a1 $end
$var wire 1 )# wr0_a1_a2 $end
$var wire 1 !# wr0_a1_na2 $end
$var wire 1 }% wr0_a2 $end
$var wire 1 9# wr0_a3 $end
$var wire 1 '& wr0_a4 $end
$var wire 1 Y# wr0_a4_a5 $end
$var wire 1 Q# wr0_a4_na5 $end
$var wire 1 /& wr0_a5 $end
$var wire 1 g" wr0_c_a0 $end
$var wire 1 _" wr0_c_na0 $end
$var wire 1 {$ wr0_enable $end
$var wire 1 w" wr0_na1_a2 $end
$var wire 1 o" wr0_na1_na2 $end
$var wire 1 1# wr0_na3 $end
$var wire 1 I# wr0_na4_a5 $end
$var wire 1 A# wr0_na4_na5 $end
$var wire 24 G& wr_dat_0 [0:23] $end
$upscope $end
$scope module array2 $end
$var wire 1 3 rd0_a0 $end
$var wire 1 5% rd0_a1 $end
$var wire 1 S rd0_a1_a2 $end
$var wire 1 K rd0_a1_na2 $end
$var wire 1 =% rd0_a2 $end
$var wire 1 c rd0_a3 $end
$var wire 1 E% rd0_a4 $end
$var wire 1 %! rd0_a4_a5 $end
$var wire 1 { rd0_a4_na5 $end
$var wire 1 M% rd0_a5 $end
$var wire 1 3 rd0_c_a0 $end
$var wire 1 + rd0_c_na0 $end
$var wire 1 %% rd0_enable $end
$var wire 1 C rd0_na1_a2 $end
$var wire 1 ; rd0_na1_na2 $end
$var wire 1 [ rd0_na3 $end
$var wire 1 s rd0_na4_a5 $end
$var wire 1 k rd0_na4_na5 $end
$var wire 1 M! rd1_a0 $end
$var wire 1 U% rd1_a1 $end
$var wire 1 m! rd1_a1_a2 $end
$var wire 1 e! rd1_a1_na2 $end
$var wire 1 ]% rd1_a2 $end
$var wire 1 }! rd1_a3 $end
$var wire 1 e% rd1_a4 $end
$var wire 1 ?" rd1_a4_a5 $end
$var wire 1 7" rd1_a4_na5 $end
$var wire 1 m% rd1_a5 $end
$var wire 1 M! rd1_c_a0 $end
$var wire 1 E! rd1_c_na0 $end
$var wire 1 -% rd1_enable $end
$var wire 1 ]! rd1_na1_a2 $end
$var wire 1 U! rd1_na1_na2 $end
$var wire 1 u! rd1_na3 $end
$var wire 1 /" rd1_na4_a5 $end
$var wire 1 '" rd1_na4_na5 $end
$var wire 24 O& rd_dat_0 [0:23] $end
$var wire 24 W& rd_dat_1 [0:23] $end
$var wire 1 g" wr0_a0 $end
$var wire 1 u% wr0_a1 $end
$var wire 1 )# wr0_a1_a2 $end
$var wire 1 !# wr0_a1_na2 $end
$var wire 1 }% wr0_a2 $end
$var wire 1 9# wr0_a3 $end
$var wire 1 '& wr0_a4 $end
$var wire 1 Y# wr0_a4_a5 $end
$var wire 1 Q# wr0_a4_na5 $end
$var wire 1 /& wr0_a5 $end
$var wire 1 g" wr0_c_a0 $end
$var wire 1 _" wr0_c_na0 $end
$var wire 1 {$ wr0_enable $end
$var wire 1 w" wr0_na1_a2 $end
$var wire 1 o" wr0_na1_na2 $end
$var wire 1 1# wr0_na3 $end
$var wire 1 I# wr0_na4_a5 $end
$var wire 1 A# wr0_na4_na5 $end
$var wire 24 _& wr_dat_0 [0:23] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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