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Placement, initial holes, and some traces.

main
Steven Roberts 1 year ago
parent
commit
bf1cfc8a41
  1. 747
      ac922interposer.kicad_pcb
  2. 35
      ac922interposer.pro

747
ac922interposer.kicad_pcb

File diff suppressed because it is too large Load Diff

35
ac922interposer.pro

@ -1,4 +1,4 @@ @@ -1,4 +1,4 @@
update=Fri 16 Apr 2021 04:21:28 PM CDT
update=Tue 20 Apr 2021 04:23:59 PM CDT
version=1
last_client=kicad
[general]
@ -26,21 +26,22 @@ ERC_TestSimilarLabels=1 @@ -26,21 +26,22 @@ ERC_TestSimilarLabels=1
version=1
PageLayoutDescrFile=
LastNetListRead=ac922interposer.net
CopperLayerCount=2
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
AllowBlindVias=1
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinTrackWidth=0.09999999999999999
MinViaDiameter=0.4
MinViaDrill=0.3
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
ViaDiameter1=0.8
ViaDrill1=0.4
TrackWidth1=0.15
TrackWidth2=0.15
ViaDiameter1=0.5
ViaDrill1=0.2
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
@ -67,19 +68,19 @@ OthersTextUpright=1 @@ -67,19 +68,19 @@ OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
Type=1
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
@ -233,14 +234,14 @@ Enabled=1 @@ -233,14 +234,14 @@ Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=1
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
TrackWidth=0.15
ViaDiameter=0.5
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2

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