Reference the OpenPOWER Foundation IPR Policy and OpenPOWER WorkGroup Process for additional term definitions.
Reference the OpenPOWER Foundation \acrshort{IPR} Policy and OpenPOWER WorkGroup Process for additional term definitions.
\begin{itemize}
\begin{enumerate}
\item
``Maintainer" is an Eligible or Non-Eligible participant of the workgroup that has been elected by Full Majority Vote to review and
approve changes to the LibreBMC code in the git repository(ies) created by this SIG.
\end{itemize}
approve changes to the LibreBMC code in the git repository(ies) created by this \acrshort{SIG}.
\end{enumerate}
\section{Description}
The LibreBMC SIG is a project workgroup whose purpose is to create a reference design of an open source Baseboard Management Controller (BMC) compatible
with the Open Compute Project (OCP) Datacenter Secure Control Module (DC-SCM) specification, named ``LibreBMC".\par
The LibreBMC \acrshort{SIG} is a project workgroup whose purpose is to create a reference design of an open source \acrfull{BMC} compatible
with the \acrfull{OCP} \acrfull{DC-SCM} specification, named ``LibreBMC".\par
The goal of the SIG is advance the state of the open source hardware community through the design and implementation of LibreBMC.
The SIG will use many open source tools and components, including open POWER ISA processor soft core,
Register-Transfer-Level (RTL) for all required BMC interfaces and controls, design and synthesis tools, PDKs, DC-SCM board reference designs and
BMC software to design and implement LibreBMC in order to contribute to their growth and usability.\par
The goal of the \acrshort{SIG} is advance the state of the open source hardware community through the design and implementation of LibreBMC.
The SIG will use many open source tools and components, including open POWER \acrshort{ISA} processor soft core, \acrfull{RTL}
for all required \acrshort{BMC} interfaces and controls, design and synthesis tools, \acrfull{PDK}'s, \acrshort{DC-SCM} board reference designs and
\acrshort{BMC} software to design and implement LibreBMC in order to contribute to their growth and usability.\par
The purpose of LibreBMC is to be a fully open source BMC design which will enhance the security of server management control by utilizing open hardware
and software, and designed with fully open source tooling.\par
The purpose of LibreBMC is to be a fully open source \acrshort{BMC} design which will enhance the security of
server management control by utilizing open hardware and software, and designed with fully open source tooling.\par
The requirement of a POWER ISA core will drive the design and open release of a new or improved POWER soft-core.
The requirement of a POWER \acrshort{ISA} core will drive the design and open release of a new or improved POWER soft-core.
\section{Scope}
The scope of the LibreBMC SIG is the creation of a functional BMC prototype.
The prototype will include a DC-SCM card design with a FPGA controller.
The FPGA image will consist of a POWER ISA core(s) that can run the OpenBMC stack (including LSB) and
The scope of the LibreBMC \acrshort{SIG} is the creation of a functional \acrshort{BMC} prototype.
The prototype will include a \acrshort{DC-SCM} card design with a \acrfull{FPGA} controller.
The \acrshort{FPGA} image will consist of a POWER \acrshort{ISA} core(s) that can run the OpenBMC stack (including \acrfull{LSB}) and
manage the interface between system-management software and platform hardware.
The FPGA image will also have all controls and interfaces required of a typical BMC.\par
The \acrshort{FPGA} image will also have all controls and interfaces required of a typical \acrshort{BMC}.\par
LibreBMC will be compatible with the OCP DC-SCM specification.
Any changes to the OCP DC-SCM specification is outside the scope of this workgroup and will be handled through OCP.\par
LibreBMC will be compatible with the \acrshort{OCP} \acrshort{DC-SCM} specification.
Any changes to the \acrshort{OCP} \acrshort{DC-SCM} specification is outside the scope of this workgroup and will be handled through \acrshort{OCP}.\par
LibreBMC should meet the requirements to manage a variety of server architectures, including but not limited to POWER, ARM, and x86 based systems.
Any changes to system reference designs or specifications to use LibreBMC are outside the scope of this workgroup.\par
@ -48,7 +48,7 @@ Any modifications of these are outside the scope of the workgroup and will be ha
\section{Similar Activities}
\begin{enumerate}
\begin{itemize}
\item
Accelerator Workgroup : may work with to define the requirements for open tooling needed to complete the implementation of LibreBMC components.
\item
@ -62,44 +62,50 @@ OpenPOWER compliant systems that will run on LibreBMC.
\item
Development Platform Workgroup : defines the reference architecture of future OpenPower systems that may incorporate and use LibreBMC to
manage the system.
\end{enumerate}
\end{itemize}
\section{Users}
Any system vendor, datacenter, or cloud that plans to use a BMC, compatible with the OCP DC-SCM form factor to manage their system.
Any third-party hardware manufacturers that choose to build BMC's compatible with the DC-SCM specification.
\begin{itemize}
\item
Any system vendor, datacenter operator, or cloud provider that plans to use a \acrshort{BMC},
compatible with the \acrshort{OCP} \acrshort{DC-SCM} form factor to manage their system.
\item
Any third-party hardware manufacturer that choose to build \acrshort{BMC}s compatible with the \acrshort{DC-SCM} specification.
\item
Any monitoring / base software vendors.
\end{itemize}
\section{Work Product}
\begin{enumerate}
\begin{itemize}
\item
FPGA RTL for a POWER ISA soft-core
\acrshort{FPGA} \acrshort{RTL} for a POWER \acrshort{ISA} soft-core
\item
FPGA RTL that includes the soft-core and all required interfaces and controls
\acrshort{FPGA} \acrshort{RTL} that includes the soft-core and all required interfaces and controls
\item
Working LibreBMC prototype
\item
Demonstration of LibreBMC managing a system
\end{enumerate}
\end{itemize}
The FPGA RTL and reference material will be open to the general public and maintained in a public git repository(ies).
The \acrshort{FPGA} \acrshort{RTL} and reference material will be open to the general public and maintained in a public git repository(ies).
\section{Projects}
\begin{enumerate}
\begin{itemize}
\item
Design an FPGA based POWER ISA soft-core capable of running OpenBMC that meets reasonable performance requirements
Design an \acrshort{FPGA} based POWER \acrshort{ISA} soft-core capable of running OpenBMC that meets reasonable performance requirements
\item
Design and build an FPGA image for LibreBMC that contains one or more of the POWER ISA soft cores, along with the required interfaces and
controls, that is capable of managing a server.
Design and build an \acrshort{FPGA} image for LibreBMC that contains one or more of the POWER \acrshort{ISA} soft cores,
along with the required interfaces and controls, that is capable of managing a server.
\item
Create required material to properly document how to recreate and use the design.
\item
Build a prototype of LibreBMC.
\item
Demonstrate the operability of LibreBMC containing the above mentioned FPGA image in a server.
\end{enumerate}
Demonstrate the operability of LibreBMC containing the above mentioned \acrshort{FPGA} image in a server.
\end{itemize}
\section{Participation}
@ -125,59 +131,59 @@ Subsequent meetings will be held bi-weekly alternating between 5p CST Wednesday
\section{Participants}
\begin{enumerate}
\begin{itemize}
\item
IBM
\begin{enumerate}
\begin{itemize}
\item
Paul Lecocq (lecocq@us.ibm.com)
\item
Paul Mackerras (pmac@au1.ibm.com)
\item
Steve Roberts (robers@us.ibm.com)
\end{enumerate}
\end{itemize}
\item
Google
\begin{enumerate}
\begin{itemize}
\item
Tim Ansel (tansell@google.com)
\end{enumerate}
\end{itemize}
\item
Antmicro
\begin{enumerate}
\begin{itemize}
\item
Michael Gielda (mgielda@antmicro.com)
\end{enumerate}
\end{itemize}
\item
Raptor Computing Systems
\begin{enumerate}
\begin{itemize}
\item
Timothy Pearson (tpearson@raptorengineering.com)
\end{enumerate}
\end{itemize}
VanTosh
\begin{enumerate}
\begin{itemize}
\item
Toshaan Bharvani (toshaan@vantosh.com)
\end{enumerate}
\end{itemize}
Yadro
\begin{enumerate}
\begin{itemize}
\item
Alexey Stepanov (a.stepanov@yadro.com)
\end{enumerate}
\end{enumerate}
\end{itemize}
\end{itemize}
\section{Balloting Approval Requirements}
While the WG aims to operate as a consensus based community from time to time a WG decision may require a vote to move a Project forward.\par
Standard WG Process applies with the following specific requirements with respect to Maintainers :
\begin{enumerate}
\begin{itemize}
\item
Election of repository Maintainer(s) will be by Full Majority Vote.
A Maintainer can be removed from their position as Maintainer by Full Majority Vote as well.
\item
The initial Maintainer(s) will be voted in prior to setting up the git repository for the project.
\end{enumerate}
\end{itemize}
\section{Member Organization Support}
@ -185,14 +191,14 @@ Member organization support will be confirmed as part of the approval process.
\section{Anticipated Contributions}
\begin{enumerate}
\begin{itemize}
\item
Power ISA Core RTL
POWER \acrshort{ISA} Core \acrshort{RTL}
\item
RTL created as part of the workgroup deliverable
\acrshort{RTL} created as part of the workgroup deliverable
