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74 lines
3.1 KiB
Markdown
74 lines
3.1 KiB
Markdown
# LPC Peripheral Overview
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This is an LPC peripheral that implements LPC IO and FW cycles so that
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it can boot a host like a POWER9. This peripheral would typically sit
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inside a BMC SoC.
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It implements the Intel Low Pin Count (LPC) spec from
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[here](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf).
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# System diagram
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```
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.
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.
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LPC LPC Clock . System Clock
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pins . LPC FW DMA
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+---------+ +------------+ +--------+ Wishbone +--------+ Wishbone
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| | | ASYNC | | | | LPC | Master
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LCLK | +---->| FIFO WR +---->| +--------->| CTRL +-------->
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------->| LPC | | | | | | |
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| Front | +------------+ | LOGIC | +--------+
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LFRAME | | . | |
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------->| | +------------+ | | +--------+
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| | | ASYNC | | | | IPMI BT|
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LAD | |<----+ FIFO RD |<----+ +--------->| FIFO |<--------
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<------>| | | | | | | | IO
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+---------+ +------------+ +--------+ LPC IO +--------+ Wishbone
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. Wishbone | UART | Slave
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. | |
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. +--------+
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. | CTRL |
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+--------+
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```
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The design translates the LPC IO accesses into a wishbone master. The
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same is done for FW accesses.
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The LPC IO wishbone master bus has devices attached to it. These
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include a an IPMI BT FIFO and standard 16550 UART. The back end of
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these can then be access by an external IO wishbone slave (which would
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typically come from the BMC CPU).
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The LPC FW wishbone master gets translated into an external wishbone
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master. This translation provides an offset and mask so the external
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wishbone master accesses occur can be controlled. Typically this
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external wishbone will be hooked into a DMA path the system bus of the
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BMC, so where this can access needs to be controlled.
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The LPC front end runs using the LPC clock. The rest of the design
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works on the normal system clock. Async FIFOs provide a safe boundary
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between the two.
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HDL is written in nmigen because that's what all the cool kids are
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doing. This is our first nmigen project, and we are software
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developers, so be kind!
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# Building
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This is designed to be integrated into some other project (like
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microwatt for libreBMC) not build as a standalone project.
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If you want the verilog, do this to produce a lpcperipheral.v
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```
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python -m lpcperipheral.lpcperipheral
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```
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# Testing
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There are an extensive set of tests in tests/. To run these do:
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```
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python -m unittest
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```
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