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---
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title: Meeting Minutes 2022-03-30
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date: 2022-03-30
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attendees:
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- toddrosedahl,ibm
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- toshaanbharvani,vantosh
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- timansell,google
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- michaelneuling,ibm
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draft: false
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---
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# LibreBMC SIG Meeting
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Meeting date: 30 March 2022
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Access link: https://zoom.us/j/91597478078
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Meeting ID: 91597478078
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# Call to Order
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### Anti-trust Reminder
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This is a reminder that all OpenPOWER Foundation activities are subject to strict compliance with the OpenPOWER Foundation’s Antitrust Guidelines. Each individual participant and attendee at this meeting is responsible for knowing the contents of the Antitrust Guidelines, and for complying with the Antitrust Guidelines. Copies of the Antitrust Guidelines are available at: [Antitrust Guidelines](https://files.openpower.foundation/s/k5Hny649q3XHSqk)
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# AGENDA
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* **Items added by Tim below:**
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* SymbiFlow is now called F4PGA (FOSS Flow For FPGA) and homed under the CHIPS Alliance;
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* New website - https://f4pga.org/
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* Announcement - https://chipsalliance.org/announcement/2022/02/18/chips-alliance-forms-f4pga-workgroup-to-accelerate-adoption-of-open-source-fpga-tooling/
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* https://chipsalliance.org/workgroups/ - https://lists.chipsalliance.org/g/f4pga-wg
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* (You might find the ["tools working group"](https://lists.chipsalliance.org/g/tools-wg) and the ["SystemVerilog working group"](https://lists.chipsalliance.org/g/sv-wg).)
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* Xilinx is contributing to the f4pga-wg workgroup;
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* https://chipsalliance.org/announcement/2022/02/03/xilinx-new-member/
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* https://www.linkedin.com/pulse/chips-alliance-fpga-interchange-format-ivo-bolsens/
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* There are also a lot of universities joining to participate.
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* **New Project Ideas from Tim:**
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* It would be great to get help with getting GHDL into conda-eda
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* https://github.com/hdl/conda-eda/issues/171
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* https://github.com/hdl/conda-eda/pull/180
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* It would be great to get help with adding POWER support into conda-eda
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* https://github.com/hdl/conda-eda/pull/3
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* It would be great to investigate "EDA Containers" for usage with LiteX
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* https://github.com/hdl/containers/issues/40
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* https://twitter.com/carlosedp
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## Hardware Update
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* Lattice ECP5 version of DC-SCM
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* Still missing some chips, but they do have the ECP5. Covid outbreak stopped chips.
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* Follow up on new hardware possabilities;
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* Lattice [Crosslink NX](https://www.latticesemi.com/Products/FPGAandCPLD/CrossLink-NX) or [Certus](https://www.latticesemi.com/Products/FPGAandCPLD/Certus-NX) (from [Lattice's Nexus FPGAs](https://www.latticesemi.com/LatticeNexus)) based design -- Google funded open source tools here for a Google project.
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* [Xilinx Artix Ultrascale+](https://www.xilinx.com/products/silicon-devices/fpga/artix-ultrascale-plus.html) -- Would still need more work done with open source tooling, but [prjuray](https://github.com/SymbiFlow/prjuray) and [interchange format is starting](https://antmicro.com/blog/2021/09/fpga-interchange-format/) to support these.
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* **Could run at 400-500Mhz (vs 100Mhz)**
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* [Xilinx Kintex 7 part](https://github.com/f4pga/prjxray/pull/1867) is progressing pretty well. More like a $15-$20 USD cost part however...
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* Antmicro are using a Kintex 7 in our [DataCenter RowHammer Tester board](https://antmicro.com/blog/2021/12/open-source-data-center-rowhammer-tester/).
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* Virtex support could be added but would need someone working on the open source tools to do this. More like >$50 USD cost part...
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## Bringup
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* AntMicro has all the HW it needs to do bring-up on the AC922.
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* They agreed to replicate the Aussie results
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* **Mikey sent Todd a brief guide to where the code is, the steps, etc.**
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* Looks good, **Todd sent this on to Antmicro asking them to replicate the results and then use these instructions as a start of the README**
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* **Todd to see if Antmicro could port microwatt into litex natively**
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## OCP DC-SCM 2.0 Working Group -- Meets bi-weekly
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* Todd to run a call with Google and some other key players to discuss our common direction for the 3.0 standard. Still WIP. Trying to define the functions/areas that we need to go after. Lots of moving parts here in the industry.
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* **Need a company that plans to implement a DC-SCM 2.0 card in order to get the standard approved.**
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## Conference Report follow ups
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* Nothing New yet. **Working on setting up meetings with microsoft and ASPEED near term.**
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## Communication / Collaboration
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* Still seem to be issues with sending iCal meeting invites.
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* Yes, this is still an issue, we have some work-arounds planned
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* Seems to add to the calendar, but puts in limited information
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* Update?
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* Standing Reminder: Everyone should be posting things into the #librebmc-sig slack channel.
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## Gateware
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Update?
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## Simulation
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* Antmicro to discuss Renode **Recap this for this audience**
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* Advantage over QEMU is the device availability in the model related to BMC functions. Temp sensors, power supplies, etc
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* Is not an RTL simulator, but would help for OpenBMC and Kernel driver debug
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* Many LiteX peripherals are supported
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* If a peripheral is not supported, it needs to be created
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* If we chose to use Renode, we need to create the list of needed peripherals vs available
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* https://renode.readthedocs.io/en/latest/introduction/supported-boards.html#supported-peripherals
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* Add Piotr Presentation link [HERE](https://about.renode.io)
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* **Todd** to send note to Piotr with information on what we would like to do with Renode and where the links are to the code/etc. **WIP**
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* Progress on MicroWatt CPU replacement (OpenPower foundation funded?)
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* OPF is funding an FPGA optimized soft core
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* Target was "VexRISCV" resource usage and performance. **Todd to schedule at a future meeting**
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## Toolchain
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Updates?
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## Software
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Updates?
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## FPGA Usage Barriers
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* List of opens (potential barriers) for using FPGAs as BMCs **Update here?**
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* Cost -- Munir to follow up
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* Soft Error Rates -- Munir to follow up
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* Hard fails roughly the same as an ASIC
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* Looks like Xilinx SER FIT is reasonable (<200).
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* And detectable and fixable with an image reload
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* **Performance? 8X slower than an ASPEED?**
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* Image size
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## Workgroup Collaboration Tools
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* [Meeting Minutes](https://meetingminutes.openpower.foundation/librebmc/)
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https://meetingminutes.openpower.foundation/librebmc/
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* Meeting invites are still not seeming to get mailed?
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* Long term TODO : Need to make the system actually sends emails with ical attachments. It will take awhile to make this work. Rather we should have interested parties import the cal and get notifications.
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* [WebSys Document](https://files.openpower.foundation/s/Sj756P5B39T7XnP)
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- OPF Discuss (with calendar and link to chat)
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https://discuss.openpower.foundation/c/sig/librebmc/11
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webcal://discuss.openpower.foundation/c/sig/librebmc/l/calendar.ics
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- Slack / IRC / Mattermost
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https://openpowerfoundation.slack.com/archives/C01UVKFKUQY
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https://chat.openpower.foundation/opf/channels/librebmc
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#librebmc on libera (namespace)
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https://chat.openpower.foundation/opf/channels/librebmc
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- OPF Files
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https://files.openpower.foundation/s/iZRseq3XLtRcjtX
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- OPF Discuss
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https://discuss.openpower.foundation/c/sig/librebmc/11
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- OPF GIT repository
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https://git.openpower.foundation/librebmc/librebmc
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Will be mirrored to github and gitlab
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- OPF Kanban (linked with chat)
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https://kanban.openpower.foundation/b/hgDqwnbiZDHFR3B3b/librebmc
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## Community Involvement
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* How do we generate more activity/interest
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* Engage Universities
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* **A Professor asked on linked in "How can me and my students contribute to this project"**
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* **What can we have them do right now?**
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* Linux-on-Litex-VexRiscV => Linux-on-Linux-Microwatt (/cc Anton)
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* Port LPC to Renode (/cc Piotr)
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* Documentation (/cc all)
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* **Todd reached out and the professor is interested. Todd will set up a special call next week. Available times/interest from the group? Help is needed to present the technical details**
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* **We need mentors to be contacts and help guide the students. No matter what we come up with for projects and no matter which method we use to get things done**
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* **Other ideas from Joel**
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* Get a working litex configuration for microwatt
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* microwatt is an option in litex, but it is not complete. Need the interrupt controller workng and linux booting
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* Add CI so we know when litex breaks
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* We have an ecosystem of :micropython, u-boot, linux.
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* All work, but only in specific configs. Documenting and testing those configurations would be a good project.
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* Define a boot loader for microwatt
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* so that it will work across configurations (arty, orangecrab)
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* Offer badges/certificates
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* Offer Bounties
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* Major League Hacking Interships
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* Start end of May.
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* Need to sign up by end of March
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* Must have sponsors to guide students and hold office hours
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* **We missed this window, but the next one starts in Sept and we will circle back on this in a month or so. We still need to think about detailed work tasks and who can be mentors**
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* To use MLH, We need BoD (Board of Directors) approval
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* **Need work items clearly identified and easily understood**
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* To enable the community, we need to do the following:
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* Documentation -- need build instructions, readme, etc
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* Need someone replicate the FPGA/OpenBMC load from scratch
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* Then document the process for others to follow
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* Toshaan said he would do this with help from Anton/Mikey
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* Todd to send him the DC-SCM board and interposer
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* Mikey to send him the ROT jumper
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* **This plan is on hold. See if Antmicro can make progres here**
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* Need small simple tasks identified
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* Can we, right now, carve out Lite-X peripherals to be ported?
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* Get the FPGA/DC-SCM card booting the AC922
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* Incorporate microwatt into lite-x natively.
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* Enable others
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* Need others to be able to re-create the results.
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* Build all pieces -- Core, peripherals, OpenBMC,etc
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* Need official OpenBMC project and a makefile, bitbake/etc
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* **Need the project broken down into manageable pieces**
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* Include the firmware into the CI infrastructure
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* Add Full FPGA support (I2C, FSI, etc) More than just bit banging:
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a. PCIe
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b. I2C
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c. USB
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d. FSI
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e. GPIOs
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f. LPC
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g. Enet
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h. Refclock
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i. CLKIN
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j. JTAG
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k. DDR
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* Add Full OpenBMC support for the AC922
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* Fork the Witherspoon OpenBMC and run it
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* Other Ideas?
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* Need LiteX-Hub support and integration
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* Add more FPGA boards supports
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* Get it running on Raspbery PI
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* It was suggested that we should have a logo for libreBMC. Any thoughts from the team. Nice to have, but should not be a focus right now.
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* **I did see an offer of help for a logo. I will follow up. TBD**
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## Making Progress
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* **IDEAS for Making Progress**
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* Incremental goal? Linux on LiteX VexRISCV like repository -- IE An example for just running a POWER Linux system on as many FPGA development boards as possible?
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* https://github.com/litex-hub/linux-on-litex-vexriscv -- >30 boards supported...
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* Repository exists - https://github.com/litex-hub/linux-on-litex-power
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* Could work on things like;
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* Improving Ethernet performance.
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* https://github.com/rprinz08/hBPF
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* https://github.com/litex-hub/pythondata-cpu-microwatt
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## Goals -- Where do we want to be in 3mo, 6mo, 1 year -- WIP
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* Tasks defined and project broken down
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* Able to generate a bitstream for an FPGA using fully open source toolchain.
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* Have RTL suitable for real production usage that has software support in the upstream OpenBMC project.
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* Someone seriously starting to do a real (non-development) LibreBMC deployment.
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* Fully functional Gateware and OpenBMC code stack for AC922
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* Determine the performance/size
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## Next Meeting
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{{< localdatetime date="2022-04-14" time="16:00" >}}
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