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---
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title: Meeting Minutes 2022-07-27
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date: 2022-07-27
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attendees:
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- toddrosedahl,ibm
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- toshaanbharvani,vantosh
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- antonblanchard,ibm
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- michaelneuling,ibm
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- lukeleighton,libre-soc
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- andrey,libre-soc
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- cesar,libre-soc
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- jacob,libre-soc
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- davidcalderwood,libre-soc
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- timpearson,raptorengineering
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- paulmackerras,ibm
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draft: false
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---
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# LibreBMC SIG Meeting
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Meeting date: 27 July 2022
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Access link: https://zoom.us/j/91597478078
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Meeting ID: 91597478078
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# Call to Order
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### Anti-trust Reminder
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This is a reminder that all OpenPOWER Foundation activities are subject to strict compliance with the OpenPOWER Foundation’s Antitrust Guidelines. Each individual participant and attendee at this meeting is responsible for knowing the contents of the Antitrust Guidelines, and for complying with the Antitrust Guidelines. Copies of the Antitrust Guidelines are available at: [Antitrust Guidelines](https://files.openpower.foundation/s/k5Hny649q3XHSqk)
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### Meeting Recording
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Meeting is being recorded
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# AGENDA
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## Introduction
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New folks this week?
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## New News
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Red Semiconductor joined OPF
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NLnet proposal being submitted before deadline 1st Aug 2022
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https://libre-soc.org/nlnet_2022_librebmc/
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Arctic Tern being released. Went over this design.
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https://www.phoronix.com/news/Raptor-Arctic-Tern
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two variants, Industrial (high-temp etc), and commercial.
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ZephyrOS runs on it, and both Libre-SOC and Microwatt can
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be used. https://bugs.libre-soc.org/show_bug.cgi?id=855
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Modules in-stock.
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https://files.openpower.foundation/s/iZRseq3XLtRcjtX?path=%2FArticTern
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https://wiki.raptorcs.com/wiki/File:Arctic_Tern_Users_Guide_Version_1.00.pdf
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Reviewed the proposal for LibreBMC to get funding. Add in secrurity features -- highlight security can be enhanced over time via an FPGA image update.
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Need to continue to discuss DC-SCM cards with Raptor for OCP.
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## Hardware Update
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* Update?
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* AM to send a DC-SCM card and interposer to Toshaan
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* **Karol is working on this**
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* Lattice ECP5 version of DC-SCM
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* Still missing ethernet Phys?
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* New hardware versions?
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* Lattice Nexus line board? Lattice previously seem interested in funding this?
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* Xilinx Artix Ultrascale?
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## Bringup
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* Any progress since last call?
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**Report from AM last week -- recap for this audience**
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* AM is using boxArty to boot the AC922
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* They made PCB verions boxarty board to connect the FPGA board to the server
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* Brought up the AC922 with that board
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* Trying to replicate the Boxarty work
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* Running the scripts to get the system booted
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* Intend to run the openBMC stack
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* Do not intend to add any further gateware
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* linux provides a bit-bang I2C driver so no need to actually add an FPGA I2C gateware engine
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* Request AM to open up this work. Karol to check on that request
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* Toshaan will help once he gets the parts
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* We are also looking at buildroot
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* We will have PowerEL ppc64sffs, which should be good enough for OpenBMC
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* Looking at u-bmc as an alternative (just looking for now)
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* Luke looking at runbmc too
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* OpenBMC remains primary goal
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* Should be up/running by Sept/Oct
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* Luke will try to get LibreSOC running in place of microwatt
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## OCP DC-SCM 2.0 Working Group -- Meets bi-weekly
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**Todd** to run a call with Google, Munir from Lattice, and some other key players to discuss our common direction for the 3.0 standard. WIP.
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* DC-SCM 2.0 Has been submitted
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## Conferences
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* **Todd** Still working to set up various follow-ups
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* **We need something new to showcase at OCP22 and SC22**
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**Overall Goal Reminder:** We want to boot an AC922 using an FPGA (not the AST2500 ASIC) on a DC-SCM card. We want to prove that the FPGA can boot a high power, modern server.
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To do this, we need the following pieces:
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1. A DC-SCM card that has an FPGA on it to replace the AST2500 ASIC
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a. Antmicro built a few of these that use Xylinx A7s. They power on, but no bring-up has been done to show they will boot the system.
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b. Antmicro is building some that have ECP5’s on them, but they are still missing some parts
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2. An interposer that will plug into the DC-SCM card and the AC922.
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a. I have 6 of these built
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3. A Root of Trust bypass jumper
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a. Plans for these are available and they are easy to build
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4. A softcore (microwatt) running on the FPGA
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a. This works, but it needs to be better incorporated with Lite-x
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b. Can use libreSOC.
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**Yes, we think so as Libre-SOC is a drop-in replacement (more or less)**
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c. Can use aspects of Kestral
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* Raptor has PCI-e connected. ECP5 based cards booting up a blackbird.
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* Runs Zephyr RTOS on microwatt. Does not run linux.
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https://www.zephyrproject.org/
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* Next step to add graphical output (framebuffer)
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* rgb-ttl driver : https://github.com/RoaLogic/vga_lcd
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lukeleighton has (2012) linux kernel driver source for this
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* DC-SCM to SO-DIMM interposer card (possibility)
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* Raptor could make a DC-SCM card and interposer to boot a Blackbird.
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* Those DC-SCM cards could also be used by LibreBMC to boot an AC922 using our interposer.
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* Still Need all gateware and OpenBMC running (and linux) per LibreBMC charter
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* Kestrel gateware could be used (eg. FSI)
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5. Full gateware in Lite-x for the target FPGA is needed such that the entire OpenBMC stack can run
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a. Some modules are done. Some not. I have the list.
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6. Full OpenBMC code running
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a. We currently power on our prototype with scripts. OpenBMC is not running.
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* OpenBMC runs YOCTO
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https://www.yoctoproject.org/
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So far we did a prototype where we used the xilinx A7 FPGA on a custom breadboard and ran microwatt and a very stripped down FPGA. We proved it could boot the AC922, but again it was very low function. We need to have it fully functional to really prove it.
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* Getting to the overall goal above by **OCP22 (Oct 18th)** seems unachievable at the current pace
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* **Other options:**
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* Show the bringup of the real DC-SCM card (A7) on the AC922. Show it can boot, but use scripts as we did prior. OpenBMC not running. Very few gateware additions.
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* Pivot to the ECP5 using OpenBMC on the DC-SCM card.
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* Gateware is all there (per Raptor)
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* lite-x, n-migen, nextpnr-ecp5, yosys. all Libre-Licensed
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* Open-Source tooling is better
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* Usable with no legal issues
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* Do a simulation only -- better to use real hardware
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* Could have 2 FPGAs
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* 1 is the BMC
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* The other FPGA could be some sort of a representation of the system
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* Implement HB on it?
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* Run QEMU?
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* Some other simulation running?
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## Communication / Collaboration
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* Calendar invites are working now it seems.
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* Cal invites did not work. Todd/Toshaan to work offline on it.
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* Standing Reminder: Everyone should be posting things into the #librebmc-sig slack channel.
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* **I created new repos on git in order to be able to point people at the information they need to get started and help out**
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* https://git.openpower.foundation/librebmc
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## Gateware
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Update?
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* Any progress on getting https://github.com/litex-hub/linux-on-litex-power used?
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* Any progress on making sure that MicroWatt works inside LiteX?
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* **No progress has been made here of late**
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## Simulation
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* Renode looks like a good option for a simulation environment for LibreBMC.
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* **Todd** to send note to Piotr with information on what we would like to do with Renode and where the links are to the code/etc. **WIP**
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## Soft Cores
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* OPF is funding an FPGA optimized POWER soft core
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* Target was "VexRISCV" resource usage and performance. **Todd to schedule a readout at a future meeting. **Toshaan to check on when they could present**
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## Toolchain
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Updates?
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## Software
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Updates?
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## FPGA Usage Barriers
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* List of opens (potential barriers) for using FPGAs as BMCs
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* Cost --
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* Projection is that will be cost competitive
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* Some things require an external chip
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* video driver, but could be added later
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* Soft Error Rates -- **Munir** to follow up
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* Hard fails roughly the same as an ASIC
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* Looks like Xilinx SER FIT is reasonable (<200).
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* And detectable and fixable with an image reload
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* Lattice to provide data on FIT rates and recovery design
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* Munir did send an email with info
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* **Performance? 8X slower than an ASPEED?**
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* **Information from Lattice**
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* much faster to BMC to boot. 2min for ASPEED. 5sec for FGPA
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* This is mostly a function of the BMC stack, the ASPEED vs FPGA, so potentially not Apples to Apples (ASPEED vs FPGA)
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* **Lattice to provide some information on this performance comparisons to ASPEED**
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* **How long will it take the system to boot on the FPGA?**
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* **Opening up of LTPI is under consideration (MIT)**
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* Image size
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* 85,000 latches ECP5
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* New chips coming. See last week's minutes
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* How to optimize image space?
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* Currently microwatt fits easily in 85,000 latches
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* https://github.com/antonblanchard/microwatt
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* our CI results are here
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* https://github.com/antonblanchard/microwatt/actions/runs/2205354319
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* https://github.com/antonblanchard/microwatt/blob/master/.github/workflows/test.yml#L70
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## Project Ideas -- Running list of areas where we could use help
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* **Near term project ideas -- things that could be worked on now**
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* Todd/Toshaan to get a page going on the OPF web page that we can point people to.
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* **This effort has been started**
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* **We will use GIT for all issues**
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* **We will have a "projects" page. We need the issues within the projects to be broken down into small pieces.**
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* **Toshaan to send Todd me an email with instructions/example on how to start**
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* Linux-on-Litex-VexRiscV => Linux-on-Litex-Microwatt (/cc Anton)
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* **Todd to talk to Joel**
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* https://github.com/litex-hub/linux-on-litex-power
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* There is a demo showing linux running on VexRiscV
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* https://github.com/litex-hub/linux-on-litex-vexriscv
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* Replicate that demo using Microwatt
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* https://antmicro.com/blog/2020/05/multicore-vex-in-litex/
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* This can be started now and questions asked/answered in the open
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* Ask questions on github or on IRC #litex channel on Libera
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* Add emulation of LPC peripheral to Renode (/cc Piotr)
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* Questions asked/answered github
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* Karol/Piotr can help as well directly
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* Get a working litex configuration for microwatt
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* microwatt is an option in litex, but it is not complete. Need the interrupt controller working and linux booting
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* Need to just try booting linux, see what breaks,and fix it
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* Joel Stanley would be a contact
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* Add Full OpenBMC support for the AC922
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* Fork the Witherspoon OpenBMC and run it -- see what breaks
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* Add Full Litex FPGA support (I2C, FSI, etc) More than just bit banging:
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* Tim did this in the past --> https://docs.google.com/document/d/10RJUk_uXhku6FTnb-WtpIDHrkrEaWdAREF4wafYzfV4/edit
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a. PCIe - https://github.com/enjoy-digital/litepcie
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b. I2C/I3C -
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c. USB - https://luna.readthedocs.io/
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d. FSI (uses I3C)
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e. GPIOs - https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/gpio.py
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f. LPC -- We have the gateware, but need integration with Litex
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g. Ethernet - https://github.com/enjoy-digital/liteeth
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h. Refclock
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i. CLKIN
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j. JTAG - https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/jtag.py
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k. DDR - https://github.com/enjoy-digital/litedram/tree/master/litedram
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l. SPI - https://github.com/litex-hub/litespi
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* Documentation (/cc all)
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* Add CI so we know when litex breaks
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* See FPGA CI from Antmicro
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* https://github.com/chipsalliance/f4pga-examples
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* https://builds.antmicro.com/results/invocations/f2f9d40b-e7d7-4dde-a3c3-4a9271a5bfaf
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* https://builds.antmicro.com/results/invocations/f2f9d40b-e7d7-4dde-a3c3-4a9271a5bfaf?target=xc7_counter_test_arty_35
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* https://builds.antmicro.com/results/invocations/f2f9d40b-e7d7-4dde-a3c3-4a9271a5bfaf?target=xc7_litex_demo_vexriscv_arty_35
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* See work from Carl Karsten <cfkarsten@gmail.com> - https://docs.google.com/document/d/1jyodwCNK-9mokDAe6X1AMhEDPW-qPeqPTHI-z9aUGVg/edit#
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* **Could point students to Carl**
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* See recent work from Enjoy Digital - https://twitter.com/enjoy_digital/status/1514192833070174208?s=20
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* We have an ecosystem of :micropython, u-boot, linux.
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* All work, but only in specific configs. Documenting and testing those configurations would be a good project.
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* Could use Zephyr
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* https://antmicro.com/blog/2021/11/renode-zephyr-dashboard-100-boards/
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* https://antmicro.com/blog/2022/03/test-driven-development-of-zephyr-micro-ros-with-renode/
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* https://antmicro.com/blog/2019/12/tflite-in-zephyr-on-litex-vexriscv/
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* Define a boot loader for microwatt
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* Make it work across configurations (arty, orangecrab)
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* **Mid-term ideas -- things that need more definition**
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* Include the firmware into the CI infrastructure
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* Need LiteX-Hub support and integration
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* Add more FPGA boards supports
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* Get it running on Raspbery PI
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* Linux on LiteX VexRISCV like repository
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* An example for just running a POWER Linux system on as many FPGA development boards as possible?
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* https://github.com/litex-hub/linux-on-litex-vexriscv -- >30 boards supported...
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* Repository exists - https://github.com/litex-hub/linux-on-litex-power
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* Improving Ethernet performance.
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* https://github.com/rprinz08/hBPF
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* **Further Project Ideas from Tim:**
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* It would be great to get help with getting GHDL into conda-eda
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* https://github.com/hdl/conda-eda/issues/171
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* https://github.com/hdl/conda-eda/pull/180
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* It would be great to get help with adding POWER support into conda-eda
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* https://github.com/hdl/conda-eda/pull/3
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* It would be great to investigate "EDA Containers" for usage with LiteX
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* https://github.com/hdl/containers/issues/40
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* https://twitter.com/carlosedp
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* **NLnet funding / Grant application idea**
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* https://nlnet.nl/entrust/
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* Libre-BMC definitely qualifies for privacy and enhanced trust
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* suggestion: proposal covers *dual* FPGAs connected back-to-back
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* one BMC client, one BMC server
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* one has Libre-BMC, but it uploads linux OS to the *other* FPGA
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* bonus points: swap in an ASPEED 2500 or Nuvoton BMC for interoperability testing
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* primary focus: keep cost down so that more people can use it / collaborate!
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* if proposal is ONLY for EUR 10,000 servers then NLnet will likely go "hmmm" and reject on the basis of "reduced benefit to users"
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* EU aspect strongly recommended but once satisfied, other people world-wide can be "pulled in" and receive funds (e.g. ADG India Group)
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* also recommend inviting 3mdeb (OPF Member, coreboot developers) to collaborate (helps satisfy EU aspect)
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* **Toshaan and Luke will work on this**
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## Workgroup Collaboration Tools
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* [Meeting Minutes](https://meetingminutes.openpower.foundation/librebmc/)
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https://meetingminutes.openpower.foundation/librebmc/
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* Meeting invites are still not seeming to get mailed?
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* Long term TODO : Need to make the system actually sends emails with ical attachments. It will take awhile to make this work. Rather we should have interested parties import the cal and get notifications.
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* [WebSys Document](https://files.openpower.foundation/s/Sj756P5B39T7XnP)
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- OPF Discuss (with calendar and link to chat)
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https://discuss.openpower.foundation/c/sig/librebmc/11
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webcal://discuss.openpower.foundation/c/sig/librebmc/l/calendar.ics
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- Slack / IRC / Mattermost
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https://openpowerfoundation.slack.com/archives/C01UVKFKUQY
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https://chat.openpower.foundation/opf/channels/librebmc
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#librebmc on libera (namespace)
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https://chat.openpower.foundation/opf/channels/librebmc
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- OPF Files
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https://files.openpower.foundation/s/iZRseq3XLtRcjtX
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- OPF Discuss
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https://discuss.openpower.foundation/c/sig/librebmc/11
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- OPF GIT repository
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https://git.openpower.foundation/librebmc/librebmc
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Will be mirrored to github and gitlab
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- OPF Kanban (linked with chat)
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https://kanban.openpower.foundation/b/hgDqwnbiZDHFR3B3b/librebmc
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## Community Involvement
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* Options for not needing an AC922
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* FPGA on both sides (emulating the HPM)
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* Raptor has such a board that has an FPGA on both sides
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* Can just use QEMU and simulate the AC922 side
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* How do we generate more activity/interest
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* Engage Universities -- **There are interested universities**
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* Todd to start a list of universities and contacts **New direction here. Todd/Toshaan to make an OPF page "Education Page" that points to these projects as well as the OpenPOWER curriculum being developed. Then we can all point our education contacts to that page. No need to list them here**
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* Need clear work breakdown. **We have this for some projects.**
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* Need Mentors. **True for Interns/MLH/etc, but many projects can be supported in the open**
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* Offer badges/certificates
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* Offer Bounties
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* Major League Hacking Interships
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* Start end of May.
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* Need to sign up by end of March
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* Must have sponsors to guide students and hold office hours
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* **We missed this window, but the next one starts in Sept and we will circle back on this in a month or so. We still need to think about detailed work tasks and who can be mentors**
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* To use MLH, We need BoD (Board of Directors) approval
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* **Need work items clearly identified and easily understood**
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* Documentation -- We need build instructions, readmes, etc
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* Need someone replicate the FPGA/OpenBMC load from scratch
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* Then document the process for others to follow so they can replicate the results
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* Build all pieces -- Core, peripherals, OpenBMC,etc
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* **Toshaan to take a crack at this now**
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* Need official OpenBMC project and a makefile, bitbake/etc
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* Need the project broken down into manageable pieces
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* It was suggested that we should have a logo for libreBMC. Any thoughts from the team. Nice to have, but should not be a focus right now.
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* **I did see an offer of help for a logo. I will follow up later. TBD**
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## Goals -- Need timelines on these -- WIP
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* Tasks defined and project broken down
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* Able to generate a bitstream for an FPGA using fully open source toolchain.
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* Have RTL suitable for real production usage that has software support in the upstream OpenBMC project.
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* Someone seriously starting to do a real (non-development) LibreBMC deployment.
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* Fully functional Gateware and OpenBMC code stack for AC922
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* Determine the performance/size
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## Next Meeting
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{{< localdatetime date="2022-08-11" time="15:00" >}}
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