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# Help GitHub correctly report the project language |
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*.v linguist-language=Verilog |
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© IBM Corp. 2020 |
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Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this |
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repository except in compliance with the License as modified. |
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You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 |
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Modified Terms: |
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1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of |
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the work of authorship in physical form. |
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2) Notwithstanding any terms to the contrary in the License, any licenses necessary for implementation of the Work that are available |
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from OpenPOWER via the Power ISA End User License Agreement (EULA) are explicitly excluded hereunder, and may be obtained from OpenPOWER |
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under the terms and conditions of the EULA. |
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Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an |
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"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language |
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governing permissions and limitations under the License. |
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Additional rights, including the ability to physically implement a softcore that is compliant with the required sections of the Power |
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ISA Specification, are available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be obtained (along with the Power |
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ISA) here: https://openpowerfoundation.org. |
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Brief explanation of modifications: |
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Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e., |
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it unambiguously permits a user to make and use the physical chip. |
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Modification 2: This modification clarifies that licenses for the Power ISA are provided via the (royalty-free) Power ISA EULA, |
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and not under this license. To prevent fragmentation of the Power ISA, the Power ISA EULA requires that Power ISA Cores be |
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licensed consistent with the terms of the Power ISA EULA. By ensuring that rights available via the Power ISA EULA are received |
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under (and subject to) the EULA, this consistency is maintained in accordance with the terms of the EULA. Any necessary additional |
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licenses for the specific Power ISA Core are granted under this modified Apache license. |
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# A2O |
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## The Project |
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This is the release of the A2O POWER processor core RTL and associated FPGA implementation (using ADM-PCIE-9V3 FPGA). |
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See [Project Info](rel/readme.md) for details. |
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## The Core |
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The [A2O core](rel/doc/A2O_UM.pdf) was created to optimize single-thread performance, and targeted 3+ GHz in 45nm technology. |
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It is a 27 FO4 implementation, with an out-of-order pipeline supporting 1 or 2 threads. It fully supports Power ISA 2.07 using Book III-E. |
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The core was also designed to support pluggable implementations of MMU and AXU logic macros. |
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This includes elimination of the MMU and using ERAT-only mode for translation/protection. |
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## The History |
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The A2O design was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution |
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(register renaming, reservation stations, completion buffer) and a store queue. |
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The A2L2 external interface is largely the same for the two cores. |
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## FPGA Implementation Notes |
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1. There are lots of knobs available for tweaking generation parameters. Very little experimentation was done to test whether they work, or the effects on area, etc. |
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2. Only single-thread generation has been done so far. The FPGA in use has very high utilization with one thread. |
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3. A2I used clk_1x and clk_2x (for some of the special arrays), but A2O also uses clk_4x. This (and possibly along with the area congestion) led to changing the clk_1x to 50MHz to lessen timing pressure |
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(both setup and hold misses). |
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### Technology Scaling |
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A comparison of the design in original technology and scaled to 7nm (SMT2, fixed-point, no MMU): |
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| |Freq |Pwr |Freq Sort|Pwr Sort|Area |Vdd | |
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|-----:|---------|-------|---------|--------|---------|-------| |
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|45nm |2.30 GHz |1.49 W | | |4.90 mm<sup>2</sup> |0.97 V | |
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| 7nm |3.90 GHz |0.79 W |4.17 GHz |0.85 W |0.31 mm<sup>2</sup> |1.1 V | |
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| 7nm |3.75 GHz |0.63 W |4.03 GHz |0.67 W |0.31 mm<sup>2</sup> |1.0 V | |
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| 7nm |3.55 GHz |0.49 W |3.87 GHz |0.52 W |0.31 mm<sup>2</sup> |0.9 V | |
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| 7nm |3.07 GHz |0.32 W |3.60 GHz |0.38 W |0.31 mm<sup>2</sup> |0.8 V | |
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| 7nm |2.40 GHz |0.20 W |3.00 GHz |0.25 W |0.31 mm<sup>2</sup> |0.7 V | |
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These estimates are based on a semicustom design in representative foundry processes (IBM 45nm/Samsung 7nm). |
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### Compliancy |
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The A2O core is compliant to Power ISA 2.07 and will need updates to be compliant with either version 3.0c or 3.1. |
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Power ISA 3.0c and 3.1 are the two Power ISA versions contributed to OpenPOWER Foundation by IBM. Changes will include: |
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* radix translation |
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* op updates, to eliminate noncompliant ones and add missing ones required for a given compliancy level |
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* various 'mode' and other changes to meet the open specification targeted compliancy level (III-E needs to be changed to III) |
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## Miscellaneous |
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1. A2O was not released as a product; the documentation was derived from A2I but is *much* less complete than the A2I version. |
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The documentation has been edited and updated where possible, but undoubtedly, there |
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remain errors vis a vis the RTL (especially likely in implementation-specific SPRs). |
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Please use 'issues' to report errors. |
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## Errata |
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1. There is a problem that is being circumvented by setting LSUCR0.DFWD=1, AND limiting the store queue size (currently at 4). While it appears |
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to be directly related to forwarding (L1 DC hit returns 0's instead of data), the store queue size also had to be limited. |
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Not debugged at this time; could be related to: |
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1. bad generation parm |
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2. bad edit for source updates related to compiling for Vivado |
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3. ??? |
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## Directory Structure |
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``` |
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src/verilog/trilib |
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src/verilog/work |
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src/vhdl |
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``` |
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``` |
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build |
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bd (project) |
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ip_cache (empty until project built) |
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ip_repo (empty until IP built/copied) |
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ip_user (IP macros to be built) |
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tcl (build scripts) |
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``` |
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``` |
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fpga |
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tcl |
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``` |
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``` |
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doc |
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core user guide, etc. |
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``` |
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## Build Process |
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### IP |
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IP is created in ip_user and copied to ip_repo for use in top level bd. |
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See build/ip_user/xxx/readme.md. |
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Core: |
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``` |
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a2o_core |
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``` |
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Core-AXI: |
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``` |
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a2l2_axi |
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``` |
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Simple card components: |
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``` |
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a2o_axi_reg |
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a2o_dbug |
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``` |
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Help Vivado attach to VIO correctly: |
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``` |
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reverserator_3 |
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reverserator_4 |
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reverserator_64 |
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``` |
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### Project |
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See build/bd/readme.md. |
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1. create project |
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2. synth/implement |
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