microwatt/fpga/clk_gen_bypass.vhd

library ieee;
use ieee.std_logic_1164.all;

entity clock_generator is
  port (
    ext_clk        : in  std_logic;
    pll_rst_in   : in  std_logic;
    pll_clk_out : out std_logic;
    pll_locked_out : out std_logic);

end entity clock_generator;

architecture bypass of clock_generator is

begin

  pll_locked_out <= pll_rst_in;
  pll_clk_out <= ext_clk;

end architecture bypass;
Add dummy clock generator 5 years ago			`library ieee;`
			`use ieee.std_logic_1164.all;`

			`entity clock_generator is`
			`port (`
Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago			`ext_clk : in std_logic;`
			`pll_rst_in : in std_logic;`
			`pll_clk_out : out std_logic;`
			`pll_locked_out : out std_logic);`
Add dummy clock generator 5 years ago
			`end entity clock_generator;`

			`architecture bypass of clock_generator is`

			`begin`

Rework SOC reset The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago			`pll_locked_out <= pll_rst_in;`
			`pll_clk_out <= ext_clk;`
Add dummy clock generator 5 years ago
			`end architecture bypass;`