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microwatt/litedram/gen-src/sdram_init/Makefile

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Makefile
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litedram: Add basic support for LiteX LiteDRAM This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
#### Directories
include variables.mak
OBJ = $(BUILD_DIR)/obj
PROGRAM = sdram_init
console: Move console files console.c goes to a new lib/ where we'll store other general utilities and console.h goes to include/ Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
OBJECTS = $(OBJ)/head.o $(OBJ)/main.o $(OBJ)/sdram.o $(OBJ)/console.o
litedram: Add basic support for LiteX LiteDRAM This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
#### Compiler
ARCH = $(shell uname -m)
ifneq ("$(ARCH)", "ppc64")
ifneq ("$(ARCH)", "ppc64le")
CROSS_COMPILE = powerpc64le-linux-gnu-
endif
endif
CC = $(CROSS_COMPILE)gcc
LD = $(CROSS_COMPILE)ld
OBJCOPY = $(CROSS_COMPILE)objcopy
#### Flags
litedram: Update to new LiteX/LiteDRAM version Things have changed a bit in upstream LiteX. LiteDRAM now exposes a wishbone for the CSRs for example. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
CPPFLAGS = -nostdinc -D__USE_LIBC
litedram: Add support for Microwatt-initialized controller This adds support for initializing the memory controller from microwatt rather than using a built-in RiscV processor. This might require some fixes to LiteX and LiteDRAM (they haven't been merged as of this commit yet). This is enabled in the shipped generated files and can be changed via modifying the generator script to pass False to "mw_init" Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../../include
litedram: Add basic support for LiteX LiteDRAM This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include)
CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks
ASFLAGS = $(CPPFLAGS) $(CFLAGS)
sw: Add full memory map to .h and use it for litedram .lds Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
LDFLAGS = -static -nostdlib -T $(OBJ)/$(PROGRAM).lds --gc-sections
litedram: Add basic support for LiteX LiteDRAM This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
#### Pretty print
litedram: Add support for Microwatt-initialized controller This adds support for initializing the memory controller from microwatt rather than using a built-in RiscV processor. This might require some fixes to LiteX and LiteDRAM (they haven't been merged as of this commit yet). This is enabled in the shipped generated files and can be changed via modifying the generator script to pass False to "mw_init" Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
ifeq ($(V),1)
litedram: Add basic support for LiteX LiteDRAM This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
define Q
$(2)
endef
else
define Q
litedram: Update to new LiteX/LiteDRAM version Things have changed a bit in upstream LiteX. LiteDRAM now exposes a wishbone for the CSRs for example. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
@echo " [$1] " $(shell basename $3)
litedram: Add basic support for LiteX LiteDRAM This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
@$(2)
endef
endif
#### Rules. This is a bit crappy, I'm sure we can do better with the
#### handling of the various path, but this will have to do
#### until I can be bothered getting my head around the finer
#### points of Makefiles
all: objdir $(OBJ)/$(PROGRAM).hex
$(OBJ)/sdram.o: $(LXSRC_DIR)/sdram.c
$(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@)
console: Move console files console.c goes to a new lib/ where we'll store other general utilities and console.h goes to include/ Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
$(OBJ)/console.o: $(SRC_DIR)/../../../lib/console.c
$(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@)
litedram: Add basic support for LiteX LiteDRAM This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
$(OBJ)/%.o : $(SRC_DIR)/%.c
$(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@)
console: Move console files console.c goes to a new lib/ where we'll store other general utilities and console.h goes to include/ Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
$(OBJ)/%.o : $(SRC_DIR)/%.S
$(call Q,AS, $(CC) $(ASFLAGS) -c $< -o $@, $@)
litedram: Add basic support for LiteX LiteDRAM This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
$(OBJ)/%.o : $(SRC_DIR)/libc/src/%.c
$(call Q,CC, $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@, $@)
sw: Add full memory map to .h and use it for litedram .lds Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
$(OBJ)/%.lds : $(SRC_DIR)/%.lds.S
$(call Q,CC, $(CC) $(CPPFLAGS) -P -E $< -o $@, $@)
litedram: Add basic support for LiteX LiteDRAM This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
LIBC_SRC := $(wildcard $(SRC_DIR)/libc/src/*.c)
LIBC_OBJ := $(patsubst $(SRC_DIR)/libc/src/%.c, $(OBJ)/%.o,$(LIBC_SRC))
$(OBJ)/libc.o: $(LIBC_OBJ)
$(call Q,LD, $(LD) -r -o $@ $^, $@)
sw: Add full memory map to .h and use it for litedram .lds Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
$(OBJ)/$(PROGRAM).elf: $(OBJECTS) $(OBJ)/libc.o $(OBJ)/$(PROGRAM).lds
litedram: Add basic support for LiteX LiteDRAM This comes in two parts: - A generator script which uses LiteX to generate litedram cores along with their init files for various boards (currently Arty and Nexys-video). This comes with configs for arty and nexys_video. - A fusesoc "generator" which uses pre-generated litedram cores The generation process is manual on purpose. This include pre-generated cores for the two above boards. This is done so that one doesn't have to install LiteX to build microwatt. In addition, the generator script or wrapper vhdl tend to break when LiteX changes significantly which happens. This is still rather standalone and hasn't been plumbed into the SoC or the FPGA toplevel files yet. At this point LiteDRAM self-initializes using a built-in VexRiscv "Minimum" core obtained from LiteX and included in this commit. There is some plumbing to generate and cores that are initialized by Microwatt directly but this isn't working yet and so isn't enabled yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
$(call Q,LD, $(LD) $(LDFLAGS) -o $@ $^, $@)
$(OBJ)/$(PROGRAM).bin: $(OBJ)/$(PROGRAM).elf
$(call Q,OC, $(OBJCOPY) -O binary -S $^ $@, $@)
$(OBJ)/$(PROGRAM).hex: $(OBJ)/$(PROGRAM).bin
$(call Q,HX, $(SRC_DIR)/bin2hex.py $^ > $@, $@)
objdir:
@mkdir -p $(OBJ)