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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity core is
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generic (
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SIM : boolean := false
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);
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port (
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clk : in std_logic;
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rst : in std_logic;
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wishbone_insn_in : in wishbone_slave_out;
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wishbone_insn_out : out wishbone_master_out;
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wishbone_data_in : in wishbone_slave_out;
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wishbone_data_out : out wishbone_master_out;
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-- Added for debug, ghdl doesn't support external names unfortunately
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registers : out regfile;
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terminate_out : out std_ulogic
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);
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end core;
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architecture behave of core is
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-- fetch signals
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signal fetch1_to_fetch2: Fetch1ToFetch2Type;
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signal fetch2_to_decode1: Fetch2ToDecode1Type;
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-- icache signals
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signal fetch2_to_icache : Fetch2ToIcacheType;
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signal icache_to_fetch2 : IcacheToFetch2Type;
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-- decode signals
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signal decode1_to_decode2: Decode1ToDecode2Type;
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signal decode2_to_execute1: Decode2ToExecute1Type;
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-- register file signals
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signal register_file_to_decode2: RegisterFileToDecode2Type;
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signal decode2_to_register_file: Decode2ToRegisterFileType;
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signal writeback_to_register_file: WritebackToRegisterFileType;
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-- CR file signals
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signal decode2_to_cr_file: Decode2ToCrFileType;
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signal cr_file_to_decode2: CrFileToDecode2Type;
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signal writeback_to_cr_file: WritebackToCrFileType;
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-- execute signals
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signal execute1_to_execute2: Execute1ToExecute2Type;
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signal execute2_to_writeback: Execute2ToWritebackType;
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signal execute1_to_fetch1: Execute1ToFetch1Type;
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-- load store signals
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signal decode2_to_loadstore1: Decode2ToLoadstore1Type;
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signal loadstore1_to_loadstore2: Loadstore1ToLoadstore2Type;
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signal loadstore2_to_writeback: Loadstore2ToWritebackType;
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-- multiply signals
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signal decode2_to_multiply: Decode2ToMultiplyType;
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signal multiply_to_writeback: MultiplyToWritebackType;
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-- local signals
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signal fetch1_stall_in : std_ulogic;
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signal fetch2_stall_in : std_ulogic;
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signal fetch2_stall_out : std_ulogic;
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signal decode1_stall_in : std_ulogic;
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signal decode2_stall_out : std_ulogic;
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signal flush: std_ulogic;
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signal complete: std_ulogic;
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signal terminate: std_ulogic;
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begin
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terminate_out <= terminate;
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fetch1_0: entity work.fetch1
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generic map (
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RESET_ADDRESS => (others => '0')
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)
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port map (
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clk => clk,
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rst => rst,
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stall_in => fetch1_stall_in,
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flush_in => flush,
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e_in => execute1_to_fetch1,
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f_out => fetch1_to_fetch2
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);
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fetch1_stall_in <= fetch2_stall_out or decode2_stall_out;
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fetch2_0: entity work.fetch2
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port map (
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clk => clk,
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rst => rst,
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stall_in => fetch2_stall_in,
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stall_out => fetch2_stall_out,
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flush_in => flush,
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i_in => icache_to_fetch2,
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i_out => fetch2_to_icache,
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f_in => fetch1_to_fetch2,
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f_out => fetch2_to_decode1
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);
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fetch2_stall_in <= decode2_stall_out;
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icache_0: entity work.icache
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generic map(
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LINE_SIZE_DW => 8,
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NUM_LINES => 16
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)
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port map(
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clk => clk,
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rst => rst,
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i_in => fetch2_to_icache,
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i_out => icache_to_fetch2,
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wishbone_out => wishbone_insn_out,
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wishbone_in => wishbone_insn_in
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);
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decode1_0: entity work.decode1
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port map (
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clk => clk,
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rst => rst,
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stall_in => decode1_stall_in,
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flush_in => flush,
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f_in => fetch2_to_decode1,
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d_out => decode1_to_decode2
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);
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decode1_stall_in <= decode2_stall_out;
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decode2_0: entity work.decode2
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port map (
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clk => clk,
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rst => rst,
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stall_out => decode2_stall_out,
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flush_in => flush,
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complete_in => complete,
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d_in => decode1_to_decode2,
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e_out => decode2_to_execute1,
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l_out => decode2_to_loadstore1,
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m_out => decode2_to_multiply,
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r_in => register_file_to_decode2,
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r_out => decode2_to_register_file,
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c_in => cr_file_to_decode2,
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c_out => decode2_to_cr_file
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);
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register_file_0: entity work.register_file
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port map (
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clk => clk,
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d_in => decode2_to_register_file,
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d_out => register_file_to_decode2,
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w_in => writeback_to_register_file,
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registers_out => registers);
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cr_file_0: entity work.cr_file
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port map (
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clk => clk,
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d_in => decode2_to_cr_file,
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d_out => cr_file_to_decode2,
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w_in => writeback_to_cr_file
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);
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execute1_0: entity work.execute1
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generic map (
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SIM => SIM
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)
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port map (
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clk => clk,
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flush_out => flush,
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e_in => decode2_to_execute1,
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f_out => execute1_to_fetch1,
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e_out => execute1_to_execute2,
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terminate_out => terminate
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);
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execute2_0: entity work.execute2
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port map (
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clk => clk,
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e_in => execute1_to_execute2,
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e_out => execute2_to_writeback
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);
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loadstore1_0: entity work.loadstore1
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port map (
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clk => clk,
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l_in => decode2_to_loadstore1,
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l_out => loadstore1_to_loadstore2
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);
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loadstore2_0: entity work.loadstore2
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port map (
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clk => clk,
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l_in => loadstore1_to_loadstore2,
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w_out => loadstore2_to_writeback,
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m_in => wishbone_data_in,
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m_out => wishbone_data_out
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);
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multiply_0: entity work.multiply
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port map (
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clk => clk,
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m_in => decode2_to_multiply,
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m_out => multiply_to_writeback
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);
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writeback_0: entity work.writeback
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port map (
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clk => clk,
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e_in => execute2_to_writeback,
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l_in => loadstore2_to_writeback,
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m_in => multiply_to_writeback,
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w_out => writeback_to_register_file,
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c_out => writeback_to_cr_file,
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complete_out => complete
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);
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end behave;
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