microwatt/litesdcard/gen-src/generate.sh

#!/bin/bash

VENDORS="xilinx"

ME=$(realpath $0)
echo ME=$ME
MY_PATH=$(dirname $ME)
echo MYPATH=$MY_PATH
PARENT_PATH=$(realpath $MY_PATH/..)
echo PARENT=$PARENT_PATH
BUILD_PATH=$PARENT_PATH/build
mkdir -p $BUILD_PATH
GEN_PATH=$PARENT_PATH/generated
mkdir -p $GEN_PATH

for i in $VENDORS
do
    TARGET_BUILD_PATH=$BUILD_PATH/$i
    TARGET_GEN_PATH=$GEN_PATH/$i
    rm -rf $TARGET_BUILD_PATH
    rm -rf $TARGET_GEN_PATH
    mkdir -p $TARGET_BUILD_PATH
    mkdir -p $TARGET_GEN_PATH

    echo "Generating $i in $TARGET_BUILD_PATH"    
    (cd $TARGET_BUILD_PATH && litesdcard_gen --vendor $i)

    cp $TARGET_BUILD_PATH/build/gateware/litesdcard_core.v $TARGET_GEN_PATH/
done
arty_a7: Add litesdcard interface This adds litesdcard.v generated from the litex/litesdcard project, along with logic in top-arty.vhdl to connect it into the system. There is now a DMA wishbone coming in to soc.vhdl which is narrower than the other wishbone masters (it has 32-bit data rather than 64-bit) so there is a widening/narrowing adapter between it and the main wishbone master arbiter. Also, litesdcard generates a non-pipelined wishbone for its DMA connection, which needs to be converted to a pipelined wishbone. We have a latch on both the incoming and outgoing sides of the wishbone in order to help make timing (at the cost of two extra cycles of latency). litesdcard generates an interrupt signal which is wired up to input 3 of the ICS (IRQ 19). Signed-off-by: Paul Mackerras <paulus@ozlabs.org> 4 years ago			`#!/bin/bash`

litesdcard: Use vendor not board type litesdcard provides a macro per vendor (eg xilinx, lattice) and not per board, so modify the fusesoc generator to take a vendor. This will make it easier to add litesdcard to more boards. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 3 years ago			`VENDORS="xilinx"`
arty_a7: Add litesdcard interface This adds litesdcard.v generated from the litex/litesdcard project, along with logic in top-arty.vhdl to connect it into the system. There is now a DMA wishbone coming in to soc.vhdl which is narrower than the other wishbone masters (it has 32-bit data rather than 64-bit) so there is a widening/narrowing adapter between it and the main wishbone master arbiter. Also, litesdcard generates a non-pipelined wishbone for its DMA connection, which needs to be converted to a pipelined wishbone. We have a latch on both the incoming and outgoing sides of the wishbone in order to help make timing (at the cost of two extra cycles of latency). litesdcard generates an interrupt signal which is wired up to input 3 of the ICS (IRQ 19). Signed-off-by: Paul Mackerras <paulus@ozlabs.org> 4 years ago
			`ME=$(realpath $0)`
			`echo ME=$ME`
			`MY_PATH=$(dirname $ME)`
			`echo MYPATH=$MY_PATH`
			`PARENT_PATH=$(realpath $MY_PATH/..)`
			`echo PARENT=$PARENT_PATH`
			`BUILD_PATH=$PARENT_PATH/build`
			`mkdir -p $BUILD_PATH`
			`GEN_PATH=$PARENT_PATH/generated`
			`mkdir -p $GEN_PATH`

litesdcard: Use vendor not board type litesdcard provides a macro per vendor (eg xilinx, lattice) and not per board, so modify the fusesoc generator to take a vendor. This will make it easier to add litesdcard to more boards. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 3 years ago			`for i in $VENDORS`
arty_a7: Add litesdcard interface This adds litesdcard.v generated from the litex/litesdcard project, along with logic in top-arty.vhdl to connect it into the system. There is now a DMA wishbone coming in to soc.vhdl which is narrower than the other wishbone masters (it has 32-bit data rather than 64-bit) so there is a widening/narrowing adapter between it and the main wishbone master arbiter. Also, litesdcard generates a non-pipelined wishbone for its DMA connection, which needs to be converted to a pipelined wishbone. We have a latch on both the incoming and outgoing sides of the wishbone in order to help make timing (at the cost of two extra cycles of latency). litesdcard generates an interrupt signal which is wired up to input 3 of the ICS (IRQ 19). Signed-off-by: Paul Mackerras <paulus@ozlabs.org> 4 years ago			`do`
			`TARGET_BUILD_PATH=$BUILD_PATH/$i`
			`TARGET_GEN_PATH=$GEN_PATH/$i`
			`rm -rf $TARGET_BUILD_PATH`
			`rm -rf $TARGET_GEN_PATH`
			`mkdir -p $TARGET_BUILD_PATH`
			`mkdir -p $TARGET_GEN_PATH`

			`echo "Generating $i in $TARGET_BUILD_PATH"`
litesdcard: Use vendor not board type litesdcard provides a macro per vendor (eg xilinx, lattice) and not per board, so modify the fusesoc generator to take a vendor. This will make it easier to add litesdcard to more boards. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 3 years ago			`(cd $TARGET_BUILD_PATH && litesdcard_gen --vendor $i)`
arty_a7: Add litesdcard interface This adds litesdcard.v generated from the litex/litesdcard project, along with logic in top-arty.vhdl to connect it into the system. There is now a DMA wishbone coming in to soc.vhdl which is narrower than the other wishbone masters (it has 32-bit data rather than 64-bit) so there is a widening/narrowing adapter between it and the main wishbone master arbiter. Also, litesdcard generates a non-pipelined wishbone for its DMA connection, which needs to be converted to a pipelined wishbone. We have a latch on both the incoming and outgoing sides of the wishbone in order to help make timing (at the cost of two extra cycles of latency). litesdcard generates an interrupt signal which is wired up to input 3 of the ICS (IRQ 19). Signed-off-by: Paul Mackerras <paulus@ozlabs.org> 4 years ago
			`cp $TARGET_BUILD_PATH/build/gateware/litesdcard_core.v $TARGET_GEN_PATH/`
			`done`