matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'dc6b1df653'
${ noResults }
microwatt/constraints/ecp5-evn.lpf

20 lines
505 B
Plaintext
Raw Normal View History Unescape Escape

Initial support for ghdl synthesis A first pass at ghdl synthesis using yosys and nextpnr. It runs hello world or micropython if the FPGA has enough block RAM (eg ECP5 85F). The hello world testcase also loops UART rx to tx in software (ie not a hardware loopback). It uses Docker images, so no software needs to be installed. If you prefer podman you can use that too. Edit Makefile.synth to configure your FPGA, JTAG device etc. To build: make -f Makefile.synth and to program: make -f Makefile.synth prog A few issues: We need to add PLL support. Right now Microwatt runs at whatever the external clock frequency is and the baud rate gets scaled by how far off 50MHz it is. This means on the ecp5-evn with a 12 MHz clock rate the baud rate is a quite strange 27650 (115200 * 50 / 12). On my OrangeCrab with a 50MHz clock the UART is 115200. It uses a large amount of resources, way more than it should. There are still some ghdl/yosys issues to be sorted out. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
LOCATE COMP "ext_clk" SITE "A10";
IOBUF PORT "ext_clk" IO_TYPE=LVCMOS33;
LOCATE COMP "ext_rst" SITE "P4";
IOBUF PORT "rst" IO_TYPE=LVCMOS33;
LOCATE COMP "uart0_txd" SITE "P3";
LOCATE COMP "uart0_rxd" SITE "P2";
IOBUF PORT "uart0_txd" IO_TYPE=LVCMOS33;
IOBUF PORT "uart0_rxd" IO_TYPE=LVCMOS33;
LOCATE COMP "led_a" SITE "A13";
LOCATE COMP "led_b" SITE "A12";
LOCATE COMP "led_c" SITE "B19";
IOBUF PORT "led_a" IO_TYPE=LVCMOS25;
IOBUF PORT "led_b" IO_TYPE=LVCMOS25;
IOBUF PORT "led_c" IO_TYPE=LVCMOS25;