microwatt/wishbone_types.vhdl

library ieee;
use ieee.std_logic_1164.all;

package wishbone_types is
    --
    -- Main CPU bus. 32-bit address, 64-bit data
    --
    constant wishbone_addr_bits : integer := 32;
    constant wishbone_data_bits : integer := 64;
    constant wishbone_sel_bits : integer := wishbone_data_bits/8;

    subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0);
    subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0);
    subtype wishbone_sel_type  is std_ulogic_vector(wishbone_sel_bits-1  downto 0);

    type wishbone_master_out is record
        adr : wishbone_addr_type;
        dat : wishbone_data_type;
        sel : wishbone_sel_type;
        cyc : std_ulogic;
        stb : std_ulogic;
        we  : std_ulogic;
    end record;
    constant wishbone_master_out_init : wishbone_master_out := (adr => (others => '0'), dat => (others => '0'), cyc => '0', stb => '0', sel => (others => '0'), we => '0');

    type wishbone_slave_out is record
        dat   : wishbone_data_type;
        ack   : std_ulogic;
        stall : std_ulogic;
    end record;
    constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', stall => '0', others => (others => '0'));

    type wishbone_master_out_vector is array (natural range <>) of wishbone_master_out;
    type wishbone_slave_out_vector is array (natural range <>) of wishbone_slave_out;

    --
    -- IO Bus to a device, 30-bit address, 32-bits data
    --
    type wb_io_master_out is record
        adr : std_ulogic_vector(29 downto 0);
        dat : std_ulogic_vector(31 downto 0);
        sel : std_ulogic_vector(3 downto 0);
        cyc : std_ulogic;
        stb : std_ulogic;
        we  : std_ulogic;
    end record;
    constant wb_io_master_out_init : wb_io_master_out := (adr => (others => '0'), dat => (others => '0'),
                                                          sel => "0000", cyc => '0', stb => '0', we => '0');

    type wb_io_slave_out is record
        dat   : std_ulogic_vector(31 downto 0);
        ack   : std_ulogic;
        stall : std_ulogic;
    end record;
    constant wb_io_slave_out_init : wb_io_slave_out := (ack => '0', stall => '0', others => (others => '0'));
end package wishbone_types;
Initial import of microwatt Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago			`library ieee;`
			`use ieee.std_logic_1164.all;`

			`package wishbone_types is`
soc: Rework interconnect This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago			`--`
			`-- Main CPU bus. 32-bit address, 64-bit data`
			`--`
Reduce wishbone address size to 32-bit For now ... it reduces the routing pressure on the FPGA This needs manual adjustment of the address decoder in soc.vhdl, at least until I can figure out how to deal with std_match Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> # Conflicts: # soc.vhdl # Conflicts: # soc.vhdl 5 years ago			`constant wishbone_addr_bits : integer := 32;`
Reformat wishbone code Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago			`constant wishbone_data_bits : integer := 64;`
dcache: Add a dcache This replaces loadstore2 with a dcache The dcache unit is losely based on the icache one (same basic cache layout), but has some significant logic additions to deal with stores, loads with update, non-cachable accesses and other differences due to operating in the execution part of the pipeline rather than the fetch part. The cache is store-through, though a hit with an existing line will update the line rather than invalidate it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago			`constant wishbone_sel_bits : integer := wishbone_data_bits/8;`
Initial import of microwatt Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago
Reformat wishbone code Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago			`subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0);`
			`subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0);`
dcache: Add a dcache This replaces loadstore2 with a dcache The dcache unit is losely based on the icache one (same basic cache layout), but has some significant logic additions to deal with stores, loads with update, non-cachable accesses and other differences due to operating in the execution part of the pipeline rather than the fetch part. The cache is store-through, though a hit with an existing line will update the line rather than invalidate it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago			`subtype wishbone_sel_type is std_ulogic_vector(wishbone_sel_bits-1 downto 0);`
Initial import of microwatt Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago
Reformat wishbone code Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago			`type wishbone_master_out is record`
			`adr : wishbone_addr_type;`
			`dat : wishbone_data_type;`
Make wishbone_master_out and wb_io_master_out match This makes it easier to parse the records in verilog because they are getting flattened into an array of bits by ghdl/yosys. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 4 years ago			`sel : wishbone_sel_type;`
Reformat wishbone code Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago			`cyc : std_ulogic;`
			`stb : std_ulogic;`
			`we : std_ulogic;`
			`end record;`
Changes for compilation with VCS: - Changing use of others in core files to satisfy VCS - Adding workaround for VCS subtype constraint inconsistencies in common.vhdl Signed-off-by: Jonathan Balkind <jbalkind@princeton.edu> 5 years ago			`constant wishbone_master_out_init : wishbone_master_out := (adr => (others => '0'), dat => (others => '0'), cyc => '0', stb => '0', sel => (others => '0'), we => '0');`
Initial import of microwatt Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago
Reformat wishbone code Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago			`type wishbone_slave_out is record`
wishbone: Add stall signal Pipelined wishbone needs it Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago			`dat : wishbone_data_type;`
			`ack : std_ulogic;`
			`stall : std_ulogic;`
Reformat wishbone code Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago			`end record;`
wishbone: Add stall signal Pipelined wishbone needs it Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago			`constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', stall => '0', others => (others => '0'));`
Initial import of microwatt Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago
wb_arbiter: Make arbiter size parametric Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago			`type wishbone_master_out_vector is array (natural range <>) of wishbone_master_out;`
			`type wishbone_slave_out_vector is array (natural range <>) of wishbone_slave_out;`

soc: Rework interconnect This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago			`--`
			`-- IO Bus to a device, 30-bit address, 32-bits data`
			`--`
			`type wb_io_master_out is record`
			`adr : std_ulogic_vector(29 downto 0);`
			`dat : std_ulogic_vector(31 downto 0);`
			`sel : std_ulogic_vector(3 downto 0);`
			`cyc : std_ulogic;`
			`stb : std_ulogic;`
			`we : std_ulogic;`
			`end record;`
arty_a7: Add litesdcard interface This adds litesdcard.v generated from the litex/litesdcard project, along with logic in top-arty.vhdl to connect it into the system. There is now a DMA wishbone coming in to soc.vhdl which is narrower than the other wishbone masters (it has 32-bit data rather than 64-bit) so there is a widening/narrowing adapter between it and the main wishbone master arbiter. Also, litesdcard generates a non-pipelined wishbone for its DMA connection, which needs to be converted to a pipelined wishbone. We have a latch on both the incoming and outgoing sides of the wishbone in order to help make timing (at the cost of two extra cycles of latency). litesdcard generates an interrupt signal which is wired up to input 3 of the ICS (IRQ 19). Signed-off-by: Paul Mackerras <paulus@ozlabs.org> 4 years ago			`constant wb_io_master_out_init : wb_io_master_out := (adr => (others => '0'), dat => (others => '0'),`
			`sel => "0000", cyc => '0', stb => '0', we => '0');`
soc: Rework interconnect This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 5 years ago
			`type wb_io_slave_out is record`
			`dat : std_ulogic_vector(31 downto 0);`
			`ack : std_ulogic;`
			`stall : std_ulogic;`
			`end record;`
soc: Don't require dram wishbones signals to be wired by toplevel Currently, when not using litedram, the top level still has to hook up "dummy" wishbones to the main dram and control dram busses coming out of the SoC and provide ack signals. Instead, make the SoC generate the acks internally when not using litedram and use defaults to make the wiring entirely optional. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 4 years ago			`constant wb_io_slave_out_init : wb_io_slave_out := (ack => '0', stall => '0', others => (others => '0'));`
Initial import of microwatt Signed-off-by: Anton Blanchard <anton@linux.ibm.com> 5 years ago			`end package wishbone_types;`