forked from cores/microwatt

2 changed files with 73 additions and 2 deletions
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library ieee; |
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use ieee.std_logic_1164.all; |
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Library UNISIM; |
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use UNISIM.vcomponents.all; |
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entity clock_generator is |
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generic ( |
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clk_period_hz : positive := 100000000); |
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port ( |
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clk : in std_logic; |
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resetn : in std_logic; |
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system_clk : out std_logic; |
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locked : out std_logic); |
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end entity clock_generator; |
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architecture rtl of clock_generator is |
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signal clkfb : std_ulogic; |
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type pll_settings_t is record |
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clkin_period : real range 0.000 to 52.631; |
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clkfbout_mult : integer range 2 to 64; |
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clkout_divide : integer range 1 to 128; |
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divclk_divide : integer range 1 to 56; |
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end record pll_settings_t; |
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function gen_pll_settings ( |
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constant freq_hz : positive) |
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return pll_settings_t is |
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begin |
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if freq_hz = 100000000 then |
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return (clkin_period => 10.0, |
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clkfbout_mult => 16, |
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clkout_divide => 32, |
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divclk_divide => 1); |
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else |
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report "Unsupported input frequency" severity failure; |
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-- return (clkin_period => 0.0, |
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-- clkfbout_mult => 0, |
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-- clkout_divide => 0, |
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-- divclk_divide => 0); |
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end if; |
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end function gen_pll_settings; |
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constant pll_settings : pll_settings_t := gen_pll_settings(clk_period_hz); |
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begin |
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pll : PLLE2_BASE |
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generic map ( |
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BANDWIDTH => "OPTIMIZED", |
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CLKFBOUT_MULT => pll_settings.clkfbout_mult, |
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CLKIN1_PERIOD => pll_settings.clkin_period, |
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CLKOUT0_DIVIDE => pll_settings.clkout_divide, |
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DIVCLK_DIVIDE => pll_settings.divclk_divide, |
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STARTUP_WAIT => "FALSE") |
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port map ( |
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CLKOUT0 => system_clk, |
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CLKOUT1 => open, |
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CLKOUT2 => open, |
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CLKOUT3 => open, |
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CLKOUT4 => open, |
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CLKOUT5 => open, |
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CLKFBOUT => clkfb, |
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LOCKED => locked, |
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CLKIN1 => clk, |
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PWRDWN => '0', |
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RST => not resetn, |
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CLKFBIN => clkfb); |
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end architecture rtl; |
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