icache/dcache: Make both caches 32 lines, 2 ways

Adding lines seems to add only little extra as the BRAMs aren't
full, 2 ways is our current comprimise to limit pressure on small
FPGAs. We could go to 64 lines for a little more, but timing is
becoming a bit too right to my linking on the tags/LRU path of
the icache, so let's leave it at 32 for now.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
jtag-port
Benjamin Herrenschmidt 5 years ago
parent 174378b190
commit 265fbf894b

@ -115,7 +115,7 @@ begin
icache_0: entity work.icache
generic map(
LINE_SIZE => 64,
NUM_LINES => 16,
NUM_LINES => 32,
NUM_WAYS => 2
)
port map(
@ -215,6 +215,11 @@ begin
);

dcache_0: entity work.dcache
generic map(
LINE_SIZE => 64,
NUM_LINES => 32,
NUM_WAYS => 2
)
port map (
clk => clk,
rst => core_rst,

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