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@ -58,6 +58,8 @@ architecture rtl of control is
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signal gpr_write_valid : std_ulogic := '0';
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signal cr_write_valid : std_ulogic := '0';
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signal gpr_c_read_in_fmt : std_ulogic_vector(5 downto 0);
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begin
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gpr_hazard0: entity work.gpr_hazard
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generic map (
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@ -91,6 +93,8 @@ begin
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stall_out => stall_b_out
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);
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gpr_c_read_in_fmt <= "0" & gpr_c_read_in;
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gpr_hazard2: entity work.gpr_hazard
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generic map (
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PIPELINE_DEPTH => PIPELINE_DEPTH
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@ -102,7 +106,7 @@ begin
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gpr_write_valid_in => gpr_write_valid,
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gpr_write_in => gpr_write_in,
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gpr_read_valid_in => gpr_c_read_valid_in,
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gpr_read_in => "0" & gpr_c_read_in,
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gpr_read_in => gpr_c_read_in_fmt,
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stall_out => stall_c_out
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);
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