forked from cores/microwatt
dmi_dtm_ecp5: Use ECP5 JTAGG for DMI
This uses the JTAGG primitive which is similar to BSCANE2. The LUT4 delay approach came from Florian and Greg in https://github.com/enjoy-digital/litex/pull/1087 Has been tested on an OrangeCrab with 48MHz sysclk FT232H up to 30MHz (though libusb/urjtag is by far the bottleneck vs the JTAG clock) Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>fpu-constant
Matt Johnston
3 years ago
parent
eb20195a10
commit
3775650df3
@ -0,0 +1,298 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.math_real.all;
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library work;
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use work.wishbone_types.all;
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entity dmi_dtm is
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generic(ABITS : INTEGER:=8;
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DBITS : INTEGER:=64);
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port(sys_clk : in std_ulogic;
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sys_reset : in std_ulogic;
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dmi_addr : out std_ulogic_vector(ABITS - 1 downto 0);
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dmi_din : in std_ulogic_vector(DBITS - 1 downto 0);
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dmi_dout : out std_ulogic_vector(DBITS - 1 downto 0);
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dmi_req : out std_ulogic;
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dmi_wr : out std_ulogic;
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dmi_ack : in std_ulogic
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-- dmi_err : in std_ulogic TODO: Add error response
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);
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end entity dmi_dtm;
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architecture behaviour of dmi_dtm is
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-- Signals coming out of the JTAGG block
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signal jtag_reset_n : std_ulogic;
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signal tdi : std_ulogic;
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signal tdo : std_ulogic;
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signal tck : std_ulogic;
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signal jce1 : std_ulogic;
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signal jshift : std_ulogic;
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signal update : std_ulogic;
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-- signals to match dmi_dtb_xilinx
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signal jtag_reset : std_ulogic;
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signal capture : std_ulogic;
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signal jtag_clk : std_ulogic;
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signal sel : std_ulogic;
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signal shift : std_ulogic;
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-- delays
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signal jce1_d : std_ulogic;
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constant TCK_DELAY : INTEGER := 8;
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signal tck_d : std_ulogic_vector(TCK_DELAY+1 downto 1);
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-- ** JTAG clock domain **
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-- Shift register
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signal shiftr : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
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-- Latched request
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signal request : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
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-- A request is present
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signal jtag_req : std_ulogic;
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-- Synchronizer for jtag_rsp (sys clk -> jtag_clk)
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signal dmi_ack_0 : std_ulogic;
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signal dmi_ack_1 : std_ulogic;
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-- ** sys clock domain **
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-- Synchronizer for jtag_req (jtag clk -> sys clk)
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signal jtag_req_0 : std_ulogic;
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signal jtag_req_1 : std_ulogic;
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-- ** combination signals
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signal jtag_bsy : std_ulogic;
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signal op_valid : std_ulogic;
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signal rsp_op : std_ulogic_vector(1 downto 0);
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-- ** Constants **
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constant DMI_REQ_NOP : std_ulogic_vector(1 downto 0) := "00";
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constant DMI_REQ_RD : std_ulogic_vector(1 downto 0) := "01";
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constant DMI_REQ_WR : std_ulogic_vector(1 downto 0) := "10";
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constant DMI_RSP_OK : std_ulogic_vector(1 downto 0) := "00";
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constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11";
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attribute ASYNC_REG : string;
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attribute ASYNC_REG of jtag_req_0: signal is "TRUE";
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attribute ASYNC_REG of jtag_req_1: signal is "TRUE";
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attribute ASYNC_REG of dmi_ack_0: signal is "TRUE";
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attribute ASYNC_REG of dmi_ack_1: signal is "TRUE";
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-- ECP5 JTAGG
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component JTAGG is
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generic (
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ER1 : string := "ENABLED";
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ER2 : string := "ENABLED"
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);
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port(
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JTDO1 : in std_ulogic;
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JTDO2 : in std_ulogic;
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JTDI : out std_ulogic;
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JTCK : out std_ulogic;
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JRTI1 : out std_ulogic;
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JRTI2 : out std_ulogic;
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JSHIFT : out std_ulogic;
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JUPDATE : out std_ulogic;
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JRSTN : out std_ulogic;
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JCE1 : out std_ulogic;
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JCE2 : out std_ulogic
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);
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end component;
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component LUT4 is
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generic (
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INIT : std_logic_vector
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);
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port(
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A : in STD_ULOGIC;
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B : in STD_ULOGIC;
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C : in STD_ULOGIC;
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D : in STD_ULOGIC;
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Z : out STD_ULOGIC
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);
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end component;
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begin
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jtag: JTAGG
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generic map(
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ER2 => "DISABLED"
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)
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port map (
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JTDO1 => tdo,
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JTDO2 => '0',
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JTDI => tdi,
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JTCK => tck,
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JRTI1 => open,
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JRTI2 => open,
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JSHIFT => jshift,
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JUPDATE => update,
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JRSTN => jtag_reset_n,
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JCE1 => jce1,
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JCE2 => open
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);
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-- JRTI1 looks like it could be connected to SEL, but
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-- in practise JRTI1 is only high briefly, not for the duration
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-- of the transmission. possibly mw_debug could be modified.
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-- The ecp5 is probably the only jtag device anyway.
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sel <= '1';
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-- TDI needs to align with TCK, we use LUT delays here.
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-- From https://github.com/enjoy-digital/litex/pull/1087
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tck_d(1) <= tck;
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del: for i in 1 to TCK_DELAY generate
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attribute keep : boolean;
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attribute keep of l: label is true;
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begin
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l: LUT4
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generic map(
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INIT => b"0000_0000_0000_0010"
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)
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port map (
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A => tck_d(i),
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B => '0', C => '0', D => '0',
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Z => tck_d(i+1)
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);
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end generate;
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jtag_clk <= tck_d(TCK_DELAY+1);
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-- capture signal
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jce1_sync : process(jtag_clk)
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begin
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if rising_edge(jtag_clk) then
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jce1_d <= jce1;
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capture <= jce1 and not jce1_d;
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end if;
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end process;
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-- latch the shift signal, otherwise
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-- we miss the last shift in
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-- (maybe because we are delaying tck?)
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shift_sync : process(jtag_clk)
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begin
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if (sys_reset = '1') then
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shift <= '0';
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elsif rising_edge(jtag_clk) then
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shift <= jshift;
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end if;
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end process;
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jtag_reset <= not jtag_reset_n;
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-- dmi_req synchronization
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dmi_req_sync : process(sys_clk)
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begin
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-- sys_reset is synchronous
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if rising_edge(sys_clk) then
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if (sys_reset = '1') then
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jtag_req_0 <= '0';
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jtag_req_1 <= '0';
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else
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jtag_req_0 <= jtag_req;
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jtag_req_1 <= jtag_req_0;
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end if;
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end if;
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end process;
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dmi_req <= jtag_req_1;
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-- dmi_ack synchronization
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dmi_ack_sync: process(jtag_clk, jtag_reset)
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begin
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-- jtag_reset is async (see comments)
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if jtag_reset = '1' then
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dmi_ack_0 <= '0';
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dmi_ack_1 <= '0';
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elsif rising_edge(jtag_clk) then
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dmi_ack_0 <= dmi_ack;
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dmi_ack_1 <= dmi_ack_0;
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end if;
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end process;
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-- jtag_bsy indicates whether we can start a new request, we can when
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-- we aren't already processing one (jtag_req) and the synchronized ack
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-- of the previous one is 0.
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--
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jtag_bsy <= jtag_req or dmi_ack_1;
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-- decode request type in shift register
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with shiftr(1 downto 0) select op_valid <=
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'1' when DMI_REQ_RD,
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'1' when DMI_REQ_WR,
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'0' when others;
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-- encode response op
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rsp_op <= DMI_RSP_BSY when jtag_bsy = '1' else DMI_RSP_OK;
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-- Some DMI out signals are directly driven from the request register
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dmi_addr <= request(ABITS + DBITS + 1 downto DBITS + 2);
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dmi_dout <= request(DBITS + 1 downto 2);
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dmi_wr <= '1' when request(1 downto 0) = DMI_REQ_WR else '0';
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-- TDO is wired to shift register bit 0
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tdo <= shiftr(0);
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-- Main state machine. Handles shift registers, request latch and
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-- jtag_req latch. Could be split into 3 processes but it's probably
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-- not worthwhile.
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--
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shifter: process(jtag_clk, jtag_reset, sys_reset)
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begin
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if jtag_reset = '1' or sys_reset = '1' then
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shiftr <= (others => '0');
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jtag_req <= '0';
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request <= (others => '0');
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elsif rising_edge(jtag_clk) then
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-- Handle jtag "commands" when sel is 1
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if sel = '1' then
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-- Shift state, rotate the register
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if shift = '1' then
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shiftr <= tdi & shiftr(ABITS + DBITS + 1 downto 1);
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end if;
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-- Update state (trigger)
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--
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-- Latch the request if we aren't already processing one and
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-- it has a valid command opcode.
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--
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if update = '1' and op_valid = '1' then
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if jtag_bsy = '0' then
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request <= shiftr;
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jtag_req <= '1';
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end if;
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-- Set the shift register "op" to "busy". This will prevent
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-- us from re-starting the command on the next update if
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-- the command completes before that.
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shiftr(1 downto 0) <= DMI_RSP_BSY;
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end if;
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-- Request completion.
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--
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-- Capture the response data for reads and clear request flag.
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--
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-- Note: We clear req (and thus dmi_req) here which relies on tck
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-- ticking and sel set. This means we are stuck with dmi_req up if
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-- the jtag interface stops. Slaves must be resilient to this.
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--
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if jtag_req = '1' and dmi_ack_1 = '1' then
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jtag_req <= '0';
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if request(1 downto 0) = DMI_REQ_RD then
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request(DBITS + 1 downto 2) <= dmi_din;
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end if;
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end if;
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-- Capture state, grab latch content with updated status
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if capture = '1' then
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shiftr <= request(ABITS + DBITS + 1 downto 2) & rsp_op;
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end if;
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end if;
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end if;
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end process;
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end architecture behaviour;
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