forked from cores/microwatt
Anton Blanchard
5 years ago
committed by
GitHub
commit
3a2c4b8978
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@ -0,0 +1,183 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity rotator is
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port (rs: in std_ulogic_vector(63 downto 0);
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ra: in std_ulogic_vector(63 downto 0);
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shift: in std_ulogic_vector(6 downto 0);
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insn: in std_ulogic_vector(31 downto 0);
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is_32bit: in std_ulogic;
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right_shift: in std_ulogic;
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arith: in std_ulogic;
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clear_left: in std_ulogic;
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clear_right: in std_ulogic;
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result: out std_ulogic_vector(63 downto 0);
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carry_out: out std_ulogic
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);
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end entity rotator;
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architecture behaviour of rotator is
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signal repl32: std_ulogic_vector(63 downto 0);
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signal rot_count: std_ulogic_vector(5 downto 0);
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signal rot1, rot2, rot: std_ulogic_vector(63 downto 0);
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signal sh, mb, me: std_ulogic_vector(6 downto 0);
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signal mr, ml: std_ulogic_vector(63 downto 0);
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signal output_mode: std_ulogic_vector(1 downto 0);
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-- note BE bit numbering
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function right_mask(mask_begin: std_ulogic_vector(6 downto 0)) return std_ulogic_vector is
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variable ret: std_ulogic_vector(63 downto 0);
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begin
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ret := (others => '0');
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for i in 0 to 63 loop
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if i >= to_integer(unsigned(mask_begin)) then
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ret(63 - i) := '1';
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end if;
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end loop;
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return ret;
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end;
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function left_mask(mask_end: std_ulogic_vector(6 downto 0)) return std_ulogic_vector is
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variable ret: std_ulogic_vector(63 downto 0);
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begin
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ret := (others => '0');
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if mask_end(6) = '0' then
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for i in 0 to 63 loop
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if i <= to_integer(unsigned(mask_end)) then
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ret(63 - i) := '1';
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end if;
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end loop;
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end if;
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return ret;
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end;
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begin
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rotator_0: process(all)
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begin
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-- First replicate bottom 32 bits to both halves if 32-bit
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if is_32bit = '1' then
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repl32 <= rs(31 downto 0) & rs(31 downto 0);
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else
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repl32 <= rs;
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end if;
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-- Negate shift count for right shifts
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if right_shift = '1' then
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rot_count <= std_ulogic_vector(- signed(shift(5 downto 0)));
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else
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rot_count <= shift(5 downto 0);
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end if;
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-- Rotator works in 3 stages using 2 bits of the rotate count each
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-- time. This gives 4:1 multiplexors which is ideal for the 6-input
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-- LUTs in the Xilinx Artix 7.
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-- We look at the low bits of the rotate count first because they will
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-- have less delay through the negation above.
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-- First rotate by 0, 1, 2, or 3
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case rot_count(1 downto 0) is
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when "00" =>
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rot1 <= repl32;
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when "01" =>
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rot1 <= repl32(62 downto 0) & repl32(63);
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when "10" =>
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rot1 <= repl32(61 downto 0) & repl32(63 downto 62);
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when others =>
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rot1 <= repl32(60 downto 0) & repl32(63 downto 61);
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end case;
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-- Next rotate by 0, 4, 8 or 12
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case rot_count(3 downto 2) is
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when "00" =>
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rot2 <= rot1;
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when "01" =>
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rot2 <= rot1(59 downto 0) & rot1(63 downto 60);
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when "10" =>
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rot2 <= rot1(55 downto 0) & rot1(63 downto 56);
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when others =>
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rot2 <= rot1(51 downto 0) & rot1(63 downto 52);
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end case;
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-- Lastly rotate by 0, 16, 32 or 48
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case rot_count(5 downto 4) is
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when "00" =>
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rot <= rot2;
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when "01" =>
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rot <= rot2(47 downto 0) & rot2(63 downto 48);
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when "10" =>
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rot <= rot2(31 downto 0) & rot2(63 downto 32);
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when others =>
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rot <= rot2(15 downto 0) & rot2(63 downto 16);
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end case;
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-- Trim shift count to 6 bits for 32-bit shifts
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sh <= (shift(6) and not is_32bit) & shift(5 downto 0);
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-- Work out mask begin/end indexes (caution, big-endian bit numbering)
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if clear_left = '1' then
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if is_32bit = '1' then
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mb <= "01" & insn(10 downto 6);
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else
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mb <= "0" & insn(5) & insn(10 downto 6);
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end if;
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elsif right_shift = '1' then
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-- this is basically mb <= sh + (is_32bit? 32: 0);
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if is_32bit = '1' then
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mb <= sh(5) & not sh(5) & sh(4 downto 0);
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else
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mb <= sh;
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end if;
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else
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mb <= ('0' & is_32bit & "00000");
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end if;
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if clear_right = '1' and is_32bit = '1' then
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me <= "01" & insn(5 downto 1);
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elsif clear_right = '1' and clear_left = '0' then
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me <= "0" & insn(5) & insn(10 downto 6);
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else
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-- effectively, 63 - sh
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me <= sh(6) & not sh(5 downto 0);
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end if;
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-- Calculate left and right masks
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mr <= right_mask(mb);
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ml <= left_mask(me);
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-- Work out output mode
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-- 00 for sl[wd]
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-- 0w for rlw*, rldic, rldicr, rldimi, where w = 1 iff mb > me
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-- 10 for rldicl, sr[wd]
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-- 1z for sra[wd][i], z = 1 if rs is negative
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if (clear_left = '1' and clear_right = '0') or right_shift = '1' then
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output_mode(1) <= '1';
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output_mode(0) <= arith and repl32(63);
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else
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output_mode(1) <= '0';
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if clear_right = '1' and unsigned(mb(5 downto 0)) > unsigned(me(5 downto 0)) then
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output_mode(0) <= '1';
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else
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output_mode(0) <= '0';
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end if;
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end if;
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-- Generate output from rotated input and masks
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case output_mode is
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when "00" =>
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result <= (rot and (mr and ml)) or (ra and not (mr and ml));
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when "01" =>
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result <= (rot and (mr or ml)) or (ra and not (mr or ml));
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when "10" =>
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result <= rot and mr;
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when others =>
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result <= rot or not mr;
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end case;
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-- Generate carry output for arithmetic shift right of negative value
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if output_mode = "11" then
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carry_out <= or (rs and not ml);
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else
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carry_out <= '0';
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end if;
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end process;
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end behaviour;
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@ -0,0 +1,269 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.glibc_random.all;
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use work.ppc_fx_insns.all;
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use work.insn_helpers.all;
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entity rotator_tb is
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end rotator_tb;
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architecture behave of rotator_tb is
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constant clk_period: time := 10 ns;
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signal ra, rs: std_ulogic_vector(63 downto 0);
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signal shift: std_ulogic_vector(6 downto 0) := (others => '0');
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signal insn: std_ulogic_vector(31 downto 0) := (others => '0');
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signal is_32bit, right_shift, arith, clear_left, clear_right: std_ulogic := '0';
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signal result: std_ulogic_vector(63 downto 0);
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signal carry_out: std_ulogic;
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begin
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rotator_0: entity work.rotator
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port map (
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rs => rs,
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ra => ra,
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shift => shift,
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insn => insn,
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is_32bit => is_32bit,
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right_shift => right_shift,
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arith => arith,
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clear_left => clear_left,
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clear_right => clear_right,
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result => result,
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carry_out => carry_out
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);
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stim_process: process
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variable behave_ra: std_ulogic_vector(63 downto 0);
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variable behave_ca_ra: std_ulogic_vector(64 downto 0);
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begin
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-- rlwinm, rlwnm
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report "test rlw[i]nm";
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ra <= (others => '0');
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is_32bit <= '1';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '1';
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rlwnm_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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insn <= x"00000" & '0' & pseudorand(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
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assert behave_ra = result
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report "bad rlwnm expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- rlwimi
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report "test rlwimi";
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is_32bit <= '1';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '1';
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rlwimi_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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ra <= pseudorand(64);
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shift <= "00" & pseudorand(5);
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insn <= x"00000" & '0' & pseudorand(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
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assert behave_ra = result
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report "bad rlwimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- rldicl, rldcl
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report "test rld[i]cl";
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '0';
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rldicl_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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insn <= x"00000" & '0' & pseudorand(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn));
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assert behave_ra = result
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report "bad rldicl expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- rldicr, rldcr
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report "test rld[i]cr";
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '1';
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rldicr_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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insn <= x"00000" & '0' & pseudorand(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn));
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--report "rs = " & to_hstring(rs);
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--report "ra = " & to_hstring(ra);
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--report "shift = " & to_hstring(shift);
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--report "insn me = " & to_hstring(insn_me(insn));
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--report "result = " & to_hstring(result);
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assert behave_ra = result
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report "bad rldicr expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- rldic
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report "test rldic";
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '1';
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rldic_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= '0' & pseudorand(6);
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insn <= x"00000" & '0' & pseudorand(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn));
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assert behave_ra = result
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report "bad rldic expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- rldimi
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report "test rldimi";
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '1';
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rldimi_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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ra <= pseudorand(64);
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shift <= '0' & pseudorand(6);
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insn <= x"00000" & '0' & pseudorand(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn));
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assert behave_ra = result
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report "bad rldimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- slw
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report "test slw";
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ra <= (others => '0');
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is_32bit <= '1';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '0';
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slw_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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wait for clk_period;
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behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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assert behave_ra = result
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report "bad slw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- sld
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report "test sld";
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '0';
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sld_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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wait for clk_period;
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behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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assert behave_ra = result
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report "bad sld expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- srw
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report "test srw";
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ra <= (others => '0');
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is_32bit <= '1';
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right_shift <= '1';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '0';
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srw_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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wait for clk_period;
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behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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assert behave_ra = result
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report "bad srw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- srd
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report "test srd";
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '1';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '0';
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srd_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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wait for clk_period;
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behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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assert behave_ra = result
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report "bad srd expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- sraw[i]
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report "test sraw[i]";
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ra <= (others => '0');
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is_32bit <= '1';
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right_shift <= '1';
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arith <= '1';
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clear_left <= '0';
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clear_right <= '0';
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sraw_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= '0' & pseudorand(6);
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wait for clk_period;
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behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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--report "rs = " & to_hstring(rs);
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--report "ra = " & to_hstring(ra);
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--report "shift = " & to_hstring(shift);
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--report "result = " & to_hstring(carry_out & result);
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assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out
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report "bad sraw expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
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end loop;
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-- srad[i]
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report "test srad[i]";
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '1';
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arith <= '1';
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clear_left <= '0';
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clear_right <= '0';
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srad_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
|
||||
shift <= pseudorand(7);
|
||||
wait for clk_period;
|
||||
behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
|
||||
--report "rs = " & to_hstring(rs);
|
||||
--report "ra = " & to_hstring(ra);
|
||||
--report "shift = " & to_hstring(shift);
|
||||
--report "result = " & to_hstring(carry_out & result);
|
||||
assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out
|
||||
report "bad srad expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
|
||||
end loop;
|
||||
|
||||
assert false report "end of test" severity failure;
|
||||
wait;
|
||||
end process;
|
||||
end behave;
|
||||
Loading…
Reference in New Issue