Multiply needs to be 16 stages to fix all timing issues

This seems dependent on the FPGA type/size, so we should probably
make it a toplevel generic, but for now this helps on the
Arty A7-35

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
jtag-port
Benjamin Herrenschmidt 5 years ago
parent 9789d258fb
commit 48e6e719d3

@ -10,7 +10,7 @@ use work.crhelpers.all;

entity multiply is
generic (
PIPELINE_DEPTH : natural := 2
PIPELINE_DEPTH : natural := 16
);
port (
clk : in std_logic;

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