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This removes logic that I added some time ago with the thought that it would enable us to do prefetching in the icache. This logic detects when the fetch address is an odd multiple of 4 and the next address in sequence from the previous cycle. In that case the instruction we want is in the output register of the icache RAM already so there is no need to do another read or any icache tag or TLB lookup. However, this logic adds complexity, and removing it improves timing, so this removes it. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>fpu-constant
2 changed files with 7 additions and 20 deletions
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