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@ -67,7 +67,14 @@ entity soc is
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LOG_LENGTH : natural := 512;
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HAS_LITEETH : boolean := false;
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UART0_IS_16550 : boolean := true;
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HAS_UART1 : boolean := false
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HAS_UART1 : boolean := false;
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ICACHE_NUM_LINES : natural := 64;
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ICACHE_NUM_WAYS : natural := 2;
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ICACHE_TLB_SIZE : natural := 64;
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DCACHE_NUM_LINES : natural := 64;
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DCACHE_NUM_WAYS : natural := 2;
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DCACHE_TLB_SET_SIZE : natural := 64;
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DCACHE_TLB_NUM_WAYS : natural := 2
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);
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port(
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rst : in std_ulogic;
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@ -260,7 +267,14 @@ begin
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HAS_BTC => HAS_BTC,
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DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
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ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
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LOG_LENGTH => LOG_LENGTH
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LOG_LENGTH => LOG_LENGTH,
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ICACHE_NUM_LINES => ICACHE_NUM_LINES,
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ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
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ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
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DCACHE_NUM_LINES => DCACHE_NUM_LINES,
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DCACHE_NUM_WAYS => DCACHE_NUM_WAYS,
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DCACHE_TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
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DCACHE_TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS
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)
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port map(
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clk => system_clk,
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