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@ -62,6 +62,15 @@ entity toplevel is
@@ -62,6 +62,15 @@ entity toplevel is
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jtag_trst : in std_ulogic; |
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jtag_tdo : out std_ulogic; |
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-- simplebus |
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simplebus_clk : out std_logic; |
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simplebus_bus_out : out std_logic_vector(7 downto 0); |
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simplebus_parity_out : out std_logic; |
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simplebus_bus_in : in std_logic_vector(7 downto 0); |
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simplebus_parity_in : in std_logic; |
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simplebus_enabled : out std_logic; |
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simplebus_irq : in std_ulogic; |
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-- Add an I/O pin to select fetching from flash on reset |
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alt_reset : in std_ulogic |
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); |
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@ -70,6 +79,71 @@ end entity toplevel;
@@ -70,6 +79,71 @@ end entity toplevel;
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architecture behaviour of toplevel is |
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-- reset signals |
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signal system_rst : std_ulogic; |
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-- simplebus wishbone connection |
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signal wb_simplebus_out : wishbone_master_out; |
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signal wb_simplebus_in : wishbone_slave_out; |
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-- simplebus split out wishbone |
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signal wb_simplebus_adr : wishbone_addr_type; |
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signal wb_simplebus_dat_o : wishbone_data_type; |
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signal wb_simplebus_cyc : std_ulogic; |
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signal wb_simplebus_stb : std_ulogic; |
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signal wb_simplebus_sel : wishbone_sel_type; |
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signal wb_simplebus_we : std_ulogic; |
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signal wb_simplebus_dat_i : wishbone_data_type; |
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signal wb_simplebus_ack : std_ulogic; |
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signal wb_simplebus_stall : std_ulogic; |
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-- simplebus I/O wishbone |
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signal wb_ext_io_in : wb_io_master_out; |
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signal wb_ext_io_out : wb_io_slave_out; |
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signal wb_ext_is_simplebus : std_ulogic; |
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-- simplebus I/O split out wishbone |
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signal wb_simplebus_ctrl_adr : std_ulogic_vector(29 downto 0); |
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signal wb_simplebus_ctrl_dat_o : std_ulogic_vector(31 downto 0); |
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signal wb_simplebus_ctrl_cyc : std_ulogic; |
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signal wb_simplebus_ctrl_stb : std_ulogic; |
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signal wb_simplebus_ctrl_sel : std_ulogic_vector(3 downto 0); |
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signal wb_simplebus_ctrl_we : std_ulogic; |
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signal wb_simplebus_ctrl_dat_i : std_ulogic_vector(31 downto 0); |
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signal wb_simplebus_ctrl_ack : std_ulogic; |
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signal wb_simplebus_ctrl_stall : std_ulogic; |
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component simplebus_host port( |
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clk : in std_logic; |
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rst : in std_logic; |
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wb_cyc : in std_logic; |
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wb_stb : in std_logic; |
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wb_we : in std_logic; |
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wb_adr : in wishbone_addr_type; |
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wb_dat_w : in wishbone_data_type; |
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wb_sel : in std_logic_vector; |
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wb_ack : out std_logic; |
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wb_stall : out std_logic; |
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wb_dat_r : out wishbone_data_type; |
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wb_ctrl_cyc : in std_logic; |
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wb_ctrl_stb : in std_logic; |
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wb_ctrl_we : in std_logic; |
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wb_ctrl_adr : in std_logic_vector(29 downto 0); |
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wb_ctrl_dat_w : in std_logic_vector(31 downto 0); |
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wb_ctrl_sel : in std_logic_vector(3 downto 0); |
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wb_ctrl_ack : out std_logic; |
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wb_ctrl_stall : out std_logic; |
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wb_ctrl_dat_r : out std_logic_vector(31 downto 0); |
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clk_out : out std_logic; |
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bus_out : out std_logic_vector(7 downto 0); |
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parity_out : out std_logic; |
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bus_in : in std_logic_vector(7 downto 0); |
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parity_in : in std_logic; |
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enabled : out std_logic |
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); |
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end component simplebus_host; |
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begin |
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system_rst <= not ext_rst when RESET_LOW else ext_rst; |
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@ -83,7 +157,7 @@ begin
@@ -83,7 +157,7 @@ begin
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CLK_FREQ => CLK_FREQUENCY, |
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HAS_FPU => HAS_FPU, |
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HAS_BTC => HAS_BTC, |
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HAS_DRAM => false, |
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HAS_DRAM => true, |
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DRAM_SIZE => 0, |
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DRAM_INIT_SIZE => 0, |
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DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE, |
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@ -136,8 +210,76 @@ begin
@@ -136,8 +210,76 @@ begin
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jtag_trst => jtag_trst, |
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jtag_tdo => jtag_tdo, |
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-- simplebus 64-bit wishbone |
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wb_dram_in => wb_simplebus_out, |
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wb_dram_out => wb_simplebus_in, |
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-- simplebus 32-bit external IO wishbone |
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wb_ext_io_in => wb_ext_io_in, |
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wb_ext_io_out => wb_ext_io_out, |
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wb_ext_is_dram_csr => wb_ext_is_simplebus, |
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ext_irq_eth => simplebus_irq, |
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-- Reset PC to flash offset 0 (ie 0xf000000) |
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alt_reset => alt_reset |
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); |
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-- simplebus wishbone |
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wb_simplebus_adr <= wb_simplebus_out.adr; |
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wb_simplebus_dat_o <= wb_simplebus_out.dat; |
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wb_simplebus_cyc <= wb_simplebus_out.cyc; |
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wb_simplebus_stb <= wb_simplebus_out.stb; |
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wb_simplebus_sel <= wb_simplebus_out.sel; |
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wb_simplebus_we <= wb_simplebus_out.we; |
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wb_simplebus_in.dat <= wb_simplebus_dat_i; |
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wb_simplebus_in.ack <= wb_simplebus_ack; |
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wb_simplebus_in.stall <= wb_simplebus_stall; |
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-- simplebus I/O wishbone |
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wb_simplebus_ctrl_adr <= wb_ext_io_in.adr; |
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wb_simplebus_ctrl_dat_o <= wb_ext_io_in.dat; |
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wb_simplebus_ctrl_cyc <= wb_ext_io_in.cyc and wb_ext_is_simplebus; |
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wb_simplebus_ctrl_stb <= wb_ext_io_in.stb and wb_ext_is_simplebus; |
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wb_simplebus_ctrl_sel <= wb_ext_io_in.sel; |
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wb_simplebus_ctrl_we <= wb_ext_io_in.we; |
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wb_ext_io_out.dat <= wb_simplebus_ctrl_dat_i; |
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wb_ext_io_out.ack <= wb_simplebus_ctrl_ack; |
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wb_ext_io_out.stall <= wb_simplebus_ctrl_stall; |
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simplebus_0: simplebus_host |
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port map( |
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clk => ext_clk, |
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rst => system_rst, |
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wb_cyc => wb_simplebus_cyc, |
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wb_stb => wb_simplebus_stb, |
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wb_we => wb_simplebus_we, |
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wb_adr => wb_simplebus_adr, |
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wb_dat_w => wb_simplebus_dat_o, |
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wb_sel => wb_simplebus_sel, |
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wb_ack => wb_simplebus_ack, |
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wb_stall => wb_simplebus_stall, |
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wb_dat_r => wb_simplebus_dat_i, |
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wb_ctrl_cyc => wb_simplebus_ctrl_cyc, |
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wb_ctrl_stb => wb_simplebus_ctrl_stb, |
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wb_ctrl_we => wb_simplebus_ctrl_we, |
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wb_ctrl_adr => wb_simplebus_ctrl_adr, |
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wb_ctrl_dat_w => wb_simplebus_ctrl_dat_o, |
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wb_ctrl_sel => wb_simplebus_ctrl_sel, |
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wb_ctrl_ack => wb_simplebus_ctrl_ack, |
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wb_ctrl_stall => wb_simplebus_ctrl_stall, |
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wb_ctrl_dat_r => wb_simplebus_ctrl_dat_i, |
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clk_out => simplebus_clk, |
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bus_out => simplebus_bus_out, |
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parity_out => simplebus_parity_out, |
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bus_in => simplebus_bus_in, |
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parity_in => simplebus_parity_in, |
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enabled => simplebus_enabled |
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); |
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end architecture behaviour; |
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